Specifications

Language Structure
2-4 VHDL Reference Manual
Entity
Entities contain the input and output definitions of the design. In VHDL
designs that contain a hierarchy of lower-level circuits, the entity
functions very much like a block symbol on a schematic. An entity
usually has one or more ports, which are analogous to the pins on a
schematic symbol. All information must flow into and out of the entity
through the ports, as shown:
library my_lib;
use my_lib.example_arithmetic.all;
entity ent is
port (a0,a1,b0,b1 : in small_int; c0,c1 : out small_int);
end ent;
Note that this example references the package defined in the previous
section to gain access to the type small_int. Each port has a mode
that defines a direction: in, out, inout, or buffer.
Modes in, out, and inout all have the obvious meanings. Ports
declared to be of type out may not be read. Therefore, the
assignment:
c1 <= c0;
would be illegal since c0 is declared to be an out port. Mode buffer is
equivalent to mode out except that the value of the port may be read
within the entity.
In addition to ports, entities may also contain generics. Generics are
similar to ports, except that they pass static information. You can use
generics to create two or more instances of an entity where the
instances behave in different ways. A common use of generics is in
gate-level modeling, where generics pass delay values into the model,
as shown:
library my_lib;
use my_lib.example_arithmetic.all;
entity ent is
generic (t_rise, t_fall : time := 5 ns);
port (a0,a1,b0,b1 : in small_int; c0,c1 : out small_int);
end ent;
The preceding example specifies a rise and fall delay using the pre-
defined type time, and gives the delays a default value of 5 ns. Note
that if you use generics when writing code for synthesis, all generic
parameters must be given default values.