Specifications

VHDL for the ABEL-HDL Designer
VHDL Reference Manual C-7
or, using the IEEE 1164 std_logic data types (which are described in
more detail in Chapter Error! Reference source not found., “Error!
Reference source not found.” and in Chapter Error! Reference
source not found., “Error! Reference source not found.”):
architecture dataflow of my_and is
signal y: std_logic;
begin
y <= a and b;
q <= y when rising_edge(clk);
end dataflow;
Note: If you intend to process your VHDL designs using synthesis or
simulation tools that do not support the IEEE 1076-1993 standard,
then you should avoid using the preceding language style to describe
registered logic.
Avoiding Unwanted Latches
When you are describing combinational or registered logic using ABEL-
HDL, you are describing the conditions under which one or more
design outputs are to be asserted with a high value. For example, you
might describe a simple multiplexer using the following ABEL-HDL
statements:
module mux
s0,s1 pin; "select inputs
a0,a1 pin; "A inputs
b0,b1 pin; "B inputs
c0,c1 pin; "C inputs
y1,y0 pin istype 'com'; "output Y
equations
[y1,y0] = [a1,a0] & [s1,s0]
# [b1,b0] & [s1,!s0]
# [c1,c0] & [!s1,s0];
end
This simple design assigns the value of outputs y1 and y0 to the
values of a1 and a0 when s1 is high and s0 is high, to b1 and b0
when s1 is high and s0 is low, and to c1 and c0 when s1 is low and
s0 is high.
As written, the function of the multiplexer is incompletely specified,
since there is no value specified for the condition in which s1 and s0
are both low. In ABEL-HDL, the default logical condition is false (low)
so the values of y1 and y0 will be a logic low when s1 and s0 are both
low.
In VHDL, however, it is not always the case that an unspecified logic
condition will result in a low value on the output. Instead, the rules of
VHDL state that an unspecified condition will result in the output
holding its state. For synthesis purposes, this rule implies that a latch
must be inserted into the circuit.