Specifications

VHDL for the ABEL-HDL Designer
C-6 VHDL Reference Manual
architecture adder_ff of add is
signal f,g: bit;
procedure dff(signal clk,d: bit;
signal q: out bit) is
begin
if clk and clk'event then
q <= d;
end if;
end;
procedure add(signal a0,a1,b0,b1: bit;
signal c0,c1 out bit) is
variable x,y : bit
begin
c0 <= b0 and a0; -- carry from bit 0
s0 <= b0 xor a0; -- sum for bit 0
c1 <= b1 xor a1; -- carry out
s1 <= b1 xor a1 xor c0; -- sum for bit 1
end;
begin
add(a0,a1,b0,b1,f,g);
dff(clk,f,c0);
dff(clk,g,c1);
end adder_ff;
Since descriptions of registered logic using procedures can become
rather unwieldy, it is often easier to use behavioral descriptions for
designs. This is done by placing the combinational logic within a
process as shown below:
architecture behavior of my_and is
begin
process(clk)
begin
if (clk and clk'event) then
y <= a and b;
end if;
end process;
q <= y;
end adder_ff;
See “Behavioral VHDL” in Chapter Error! Reference source not
found., “Error! Reference source not found.” for more information.
An alternative method of describing a concurrent registered
assignment (using features of the VHDL 1076-1993 standard) is to use
a selected signal assignment such as the following:
architecture dataflow of my_and is
signal y: Boolean;
begin
y <= a and b;
q <= y when clk and clk'event;
end dataflow;