Specifications

VHDL for the ABEL-HDL Designer
C-2 VHDL Reference Manual
port (pin_list: [mode] type [; pin_list: [mode] type ...]);
The mode of a port in VHDL describes its dataflow direction. A port's
mode can be in, out, buffer, or inout. The default mode is in. (It is
good VHDL coding practice to include in for all input ports.) There is no
equivalent in ABEL-HDL to mode. Pin declarations in ABEL-HDL do not
indicate whether signals are inputs, outputs, or bidirectional. In ABEL-
HDL, direction information is determined by how the declared signals
are actually used in the design.
The following program segment illustrates simple design I/O in VHDL.
This example describes a circuit element with inputs a, b, and sel, and
output c. a, b and c are 6-bit data types that can transmit data
corresponding to the integer values 0 through 63.
entity ent1 is
port (a,b: std_logic_vector (0 to 5); sel: std_logic;
c: out std_logic_vector(0 to 5);
end ent1;
Note: Unlike ABEL-HDL, VHDL is not case-sensitive. In VHDL,
ABC=AbC=abc. You should be aware, however, that some device -
specific ("back-end") programs are case sensitive, so you should
choose signal (and other) names that do not rely on case sensitivity or
insensitivity.
Pin and Node Numbers
Describing Pin Numbers in ABEL-HDL
In ABEL-HDL pin declarations, actual pin numbers can be specified in
the pin declarations, as in
clk, clr, Dir, OE pin 1,2,3,11;
Describing Pin and Node Numbers in VHDL
VHDL does not have a language equivalent that allows pin number
declarations, so special signal attributes are used to pass pin and node
number information through the VHDL Synthesizer.
Note: You specify pin and node numbers in the VHDL source file using
the custom attribute pinnum. This special attribute is recognized by the
VHDL synthesizer and is written to the output for use by device fitting
software. For more information on the pinum attribute, refer to the
online help for VHDL.
The following example (the entity portion of a VHDL version of the
standard ABEL-HDL example cntbuf.abl) shows how to use port and
attribute statements in VHDL to make pin assignments. Figure C-1 is
the block diagram.