Specifications

VHDL Reference Manual C-1
C. VHDL for the ABEL-HDL
Designer
This Appendix compares ABEL-HDL and VHDL design strategies and is
intended for the experienced ABEL-HDL designer who has little or no
experience with VHDL. Included in this chapter are the following
topics:
• Design Input/Output
• Pin Numbers
• Combinational Logic
• Sequential Logic
• Registers
• State Machines
Design I/O
Describing Design I/O in ABEL-HDL
In ABEL-HDL, you use the pin keyword to declare input and output
signals that correspond to device I/O pins:
Clock, !Reset, S1 pin istype 'REG';
This statement specifies that the three signals (Clock, Reset and S1)
are all registered. Information about whether individual signals are
inputs or outputs not included in an ABEL pin declaration statement,
but is instead implied in the way that the signals are used in
subsequent design descriptions (such as equations).
Describing Design I/O in VHDL
In VHDL, you describe design I/O using port statements within an
entity declaration. A port statement is similar to a pinout description
for a circuit element: each pin has a type of data (value) associated
with it, and a flow direction (mode) associated with that data.
Correspondingly, each entry in a VHDL port statement has a mode and
value associated with it. The port statement has the following syntax: