Specifications

VHDL Quick Reference
A-6 VHDL Reference Manual
-- GENERATE STATEMENT
label4 : -- label required
for i in 0 to 9 generate
-- concurrent statements
if i /= 0 generate
-- concurrent statements
sig(i) <= sig(i-1);
end generate;
end generate;
-- COMPONENT INSTANTIATION
-- label is required
-- positional association
U1 : decode port map (instr, rd, wr);
-- named association
U2 : decode port map (r=> rd, op => instr, w=> wr);
-- CONDITIONAL SIGNAL ASSIGNMENT
total <= x + y;
sum <= total + 1 when increment else total -1;
-- SELECTED SIGNAL ASSIGNMENT;
with reg_select select
enable <= "0001" when "00",
"0010" when "01",
"0100" when "10",
"1000" when "11";