Specifications

VHDL Quick Reference
VHDL Reference Manual A-5
Concurrent Statements
-- BLOCK STATEMENT
label5 : -- label is required
block
-- type, signal,constant,subprogram declarations
begin
-- concurrent statements
end block;
-- PROCESS STATEMENT , sequential first form
label3 : -- label is optional
process
-- type, variable,constant,subprogram declarations
begin
wait until clock1;
-- sequential statements
end process;
-- PROCESS STATEMENT , sequential second form
process ( en1, en2, clk) -- ALL signals used in
-- process
-- type, variable,constant,subprogram declarations
begin
if clk then
-- sequential statements
local <= en1 and en2;
-- sequential statements
end if;
end process;
-- PROCESS STATEMENT , combinational
process ( en1, en2, reset ) -- ALL signals used in
-- process
-- type, variable,constant,subprogram declarations
begin
-- sequential statements
local <= en1 and en2 and not reset;
-- sequential statements
end process;