Specifications

VHDL Quick Reference
VHDL Reference Manual A-3
Sequential Statements
--IF STATEMENT
if increment and not decrement then
count := count +1;
elsif not increment and decrement then
count := count -1;
elsif increment and decrement then
count := 0;
else
count := count;
end if;
--CASE STATEMENT
case day is
when Saturday to Sunday =>
work := false;
work_out := false;
when Monday | Wednesday | Friday =>
work := true;
work_out := true;
when others =>
work := true;
work_out := false;
end case;
-- LOOP,NEXT,EXIT STATEMENTS
L1 : for i in 0 to 9 loop
L2 : for j in opcodes loop
for k in 4 downto 2 loop -- loop label is optional
if k = i next L2; -- go to next L2 loop
end loop;
exit L1 when j = crash; -- exit loop L1
end loop;
end loop;
-- WAIT STATEMENT
wait until clk;
-- VARIABLE ASSIGNMENT STATEMENT
var1 := a or b or c;
-- SIGNAL ASSIGNMENT STATEMENT
sig1 <= a or b or c;