Specifications

VHDL Quick Reference
A-2 VHDL Reference Manual
VHDL Syntax Basics
The following code fragments illustrate the syntax of VHDL statements:
Declarations
-- OBJECTS
constant alpha : character := 'a';
variable total : integer ;
variable sum : integer := 0;
signal data_bus : bit_vector (0 to 7);
-- TYPES
type opcodes is (load,store,execute,crash);
type small_int is range 0 to 100;
type big_bus is array ( 0 to 31 ) of bit;
type glob is record
first : integer;
second : big_bus;
other_one : character;
end record;
-- SUBTYPES
subtype shorter is integer range 0 to 7;
subtype smaller_int is small_int range 0 to 7;
Names
-- Array element
big_bus(0)
-- Record element
record_name.element