Specifications

How to Manage VHDL Design Hierarchies
VHDL Reference Manual 6-11
The generics library is also provided in source file form in the
generic\vhdl subdirectory, but this file (generics.vhd) is not used
during processing for simulation or for synthesis. It is only provided for
your information.
An example of how to map the generics library during simulation can
be found in the tutorials chapter in the VHDL Entry manual, in the final
tutorial example (prep2).
How Schematics Are Processed For VHDL Simulation
When creating a VHDL functional simulation model from a schematic,
the Project Navigator reads the schematic file and generates a VHDL
source file corresponding to a netlist representing all wires,
components and block symbols on the schematic. To create a VHDL
source file, the Project Navigator’s netlist generator must assign valid
VHDL data types to all wires and busses used on the schematic, and
assign matching data types to the ports of all components and blocks
used on the schematic.
By default, the data types used are std_logic and std_logic_vector.
These data types are specified in a configuration file (vhdl.ini), and
can be modified if needed. It is strongly recommended, however, that
you standardize on the std_logic and std_logic_vector data types
for all schematic/VHDL interfaces.
Note: The Project Navigator allows schematics containing references
to generic symbols (such as G_DEC or G_MUX21) to be functionally
simulated using the VHDL simulator. The generics library included
with the VHDL option contains VHDL descriptions (models) for each
generic symbol. If you are using device-specific symbols (such as the
Xilinx TBUF internal tri-state or OSC oscillator), refer to your device kit
documentation for information about which symbols are supported in
VHDL simulation, and for information on how to access these model
libraries during simulation.