Specifications

How to Manage VHDL Design Hierarchies
6-10 VHDL Reference Manual
• The names that you use in your schematic for net or instance
names must be valid VHDL identifiers. Refer to the rules for VHDL
identifier names, and check the list of VHDL keywords provided in
Appendix A if you are unsure if a particular name is a valid VHDL
identifier. Avoid using underscore (’_’) characters at the beginning
or end of names, as this is not allowed in VHDL names.
• To allow simulation to work properly on post-route models, you
should avoid using arrays (busses) on the top-level schematic for
your design. Instead, you should provide single-bit I/O signals, and
refer to these signals in your test bench.
The Using Schematics with VHDL tutorial in the VHDL Entry manual
provides an example of using a top-level schematic with lower-level
VHDL source files.
Using Lower-Level Schematics With VHDL
In most cases, you can mix higher-level VHDL sources with lower-level
schematics representing portions of your design. (Check your device
kit documentation for restrictions.) When you are referencing a lower-
level schematic module from VHDL, you do not need to specify any
special attributes or flag the external component in any special way
within the VHDL source file. When the VHDL synthesizer encounters a
component instantiation within a VHDL file that has no corresponding
lower-level VHDL entity declaration, it will simply create a reference to
the missing module in the generated Open-ABEL 2 format intermediate
file. The Project Navigator will then attempt to resolve the hierarchy by
looking for an appropriately named source file (either schematic or
VHDL) in the current project. If the Project Navigator is unable to
resolve the hierarchy reference, it will display a warning icon with the
name of the missing module.
Note: If you are referencing a lower-level component that is not
represented by a lower-level schematic or VHDL file, and is instead a
hard or soft macro defined by the device kit chosen, then you must use
the macrocell attribute (described in the next section of this chapter)
to specify that the synthesizer should make an external reference to
the module.
Using Generic Symbols With VHDL
When you use the VHDL simulator to simulate a design schematic that
includes generic symbols (such as the MUX symbol used in the prep2
tutorial design), you must provide the simulator with information
about the function of the generic symbols. To do this, you must
reference the generics library provided with the Project Navigator,
using the Library Mapping menu item in the simulator. The generics
library (which can be found in compiled form in the
generic\vhdl\generics installation subdirectory) contains functional
models for all of the generic symbols provided with the schematic
editor.