User Guide

Fi
g
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Figure 1-1 Optimization Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Figure 2-1 Diode Biasing Design Example . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Figure 2-2 “Phase One: Developing the Design” Design Flow . . . . . . . . . . . . . . . 2-4
Figure 2-3 “Phase Two: Setting Up the Optimization” Design Flow . . . . . . . . . . . . 2-6
Figure 2-4 “Phase Three: Running an Optimization” Design Phase . . . . . . . . . . . . 2-11
Figure 2-5 PSpice Optimizer Automatic Optimization Process . . . . . . . . . . . . . . . 2-13
Figure 2-6 Optimization Results for the Diode Design Example . . . . . . . . . . . . . . 2-14
Figure 2-7 Results after Adding the Power Constraint . . . . . . . . . . . . . . . . . . . 2-16
Figure 2-8 Results after Changing the Constraint Type . . . . . . . . . . . . . . . . . . . 2-17
Figure 2-9 Report Summary for the Diode Optimization . . . . . . . . . . . . . . . . . . 2-19
Figure 2-10 Updated Diode Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
Figure 3-1 The PSpice Optimizer Window . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
Figure 3-2 Example of a Specification Box . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
Figure 3-3 Example of a Parameter Box . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
Figure 3-4 Sample Format for an External Specification . . . . . . . . . . . . . . . . . . 3-14
Figure 3-5 Sample Excerpt from a Report . . . . . . . . . . . . . . . . . . . . . . . . . 3-27
Figure 3-6 Sample Excerpt from a Log File . . . . . . . . . . . . . . . . . . . . . . . . . 3-28
Figure 3-7 Sample Derivative Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28
Figure 4-1 Resistive Terminator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Figure 4-2 Global and Local Minima of a Function . . . . . . . . . . . . . . . . . . . . . 4-8
Figure 4-3 Hypothetical Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
Figure 4-4 Hypothetical Data Glitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
Figure 5-1 Resistive Terminator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Figure 5-2 Schematic for the Terminator Example, term.sch . . . . . . . . . . . . . . . . 5-3
Figure 5-3 Optimization Results for the Passive Terminator Example . . . . . . . . . . . 5-12
Figure 6-1 Schematic for the Active Filter Example, bpf.sch . . . . . . . . . . . . . . . . 6-2
Figure 6-2 Optimized Values for the Active Filter Example . . . . . . . . . . . . . . . . 6-8
Figure 7-1 Schematic for CMOS Amplifier Example, m2.sch . . . . . . . . . . . . . . . 7-2
Figure 7-2 Updated Performance Values for the Amplifier Example . . . . . . . . . . . . 7-8
Figure 7-3 Optimized Values for the Amplifier Example . . . . . . . . . . . . . . . . . . 7-9
Figure 8-1 Schematic for the BJT Model Fitting Example . . . . . . . . . . . . . . . . . 8-3
Figure 8-2 Initial Traces for the Ic and Ib Parameters . . . . . . . . . . . . . . . . . . . . 8-9