User Guide

Introduction
Microsemi Proprietary and Confidential UG0935 User Guide Revision 2.0 3
2.5 DisplayPort Tx IP Architecture
The following figure shows the DisplayPort Tx IP implementation.
Figure 1 • DisplayPort Tx IP Implementation
As shown in the preceding figure, DisplayPort Tx IP includes the Pixel Steering module, Lane transmitter
module, Scrambler module, and AUX_CH module.
Pixel Steering assigns input pixels to DisplayPort lanes. The lane transmitter module generates a video
data stream with blank data or training data. Scrambler scrambles the lane transmission data. AUX_CH
module transmits the AUX Request command to the DisplayPort Sink device or receives AUX Reply from
the DisplayPort Sink device.
Lane
Multiplexer
Scrambler
Scrambler
Scrambler
Scrambler
Aux
receiver
Aux
transmitter
Aux
decoder
Aux
encoder
aux_io_rx
Registers
HPD
Detection
Async
FIFO
Pixel
Steering
Lane
Multiplexer
Lane
Multiplexer
Lane
Multiplexer
Lane controller
Lane Transmitter
Inter
lane
skew
aux_io_tx
AUX_CH