User Guide

Introduction
Microsemi Proprietary and Confidential UG0935 User Guide Revision 2.0 2
2 Introduction
2.1 Overview
DisplayPort IP is targeted for the PolarFire FPGA application and includes DisplayPort Tx IP and
DisplayPort Rx IP. These two IP implement part of the DisplayPort 1.4 Link Layer function.
2.2 Key Features
The key features of DisplayPort Tx and Rx IP are listed as follows:
• Support 1, 2, or 4 lanes.
• Support 8 bpc RGB/YCbCr 4:4:4 (24 bits per pixel).
• Support up to 8.1 Gbps per lane.
• Support DisplayPort 1.4 protocol.
• Only support a single video stream or SST mode, and the MST mode is not supported.
• Audio transmission is not supported.
2.3 Supported Families
• PolarFire
®
SoC
• PolarFire
®
• RTG4™
• IGLOO
®
2
• SmartFusion
®
2
2.4 License
DisplayPort IP clear RTL is license locked and the obfuscated RTL available for free.
2.4.1 Obfuscated
Complete RTL code is provided for the core, allowing the core to be instantiated with the SmartDesign
tool. Simulation, synthesis, and layout can be performed within Libero
®
System-on-Chip (SoC). The RTL
code for the core is obfuscated.
2.4.2 RTL
Complete RTL source code is provided for the core.