User Guide

DisplayPort Rx IP Configuration
Microsemi Proprietary and Confidential UG0935 User Guide Revision 2.0 18
0x012C [7:0] AUX_Rx_Request_Length RO 0x00 The number of bytes in the received AUX
Request transaction
0x0140 [0] HPD_Status RW 0x0 Set HPD output value
0x0144 [0] Send_HPD_IRQ RW 0x0 Write to 1 to send a HPD interrupt
0x0148 [19:0] HPD_IRQ_Width RW 0x249F0 Defines the HPD IRQ low-active pulse width
in aux_clk_i cycles
0x0180 [0] IntMask_Total_Interrupt RW 0x1 Interrupt Mask: total interrupt
0x0184 [1] IntMask_NewAuxRequest RW 0x1 Interrupt Mask: Received new AUX
Request
[0] IntMask_TxAuxDone RW 0x1 Interrupt Mask: Transmit AUX Reply done
0x01A0 [15] Int_TotalInt RC 0x0 Interrupt: total interrupt
[1] Int_NewAuxRequest RC 0x0 Interrupt: Received new AUX Request
[0] Int_TxAuxDone RC 0x0 Interrupt: Transmit AUX Reply done
0x01D4 [31:16] Video_Output_LineNum RO 0x0 The number of lines in an output video
frame
[15:0] Video_Output_PixelNum RO 0x0 The number of pixels in an output video line
0x01F0 [21] Video_LineNum_Unlock RC 0x0 1 means output video frame lines number is
not locked
[5] Video_PixelNum_Unlock RC 0x0 1 means output video pixels number is not
locked
Table 7 • DisplayPort Rx IP Registers (continued)
Address Bits Name Type Default Description