User Guide

DisplayPort Rx IP Configuration
Microsemi Proprietary and Confidential UG0935 User Guide Revision 2.0 16
When the source device is sending TPS3/TPS4 (Source device writes DPCD_0x0102 to indicates
TPS3/TPS4 transmission), software should do the following steps to check if training is done:
1. Write enabled lanes number into register 0x0000.
2. Write 0x00 into register 0x0014 to disable descrambler for TPS3. Write 0x01 to enable descrambler
for TPS4.
3. Waiting until Source device reading DPCD_0x0202 and DPCD_0x0203 DPCD registers.
4. Read register 0x0038 to know if DisplayPort Rx IP lanes received TPS3. Set LANEx_EQ_DONE to
1 when received TPS3.
5. Read register 0x0018 to know if all lanes are aligned. Set INTERLANE _ALIGN_DONE to 1 if all
lanes are aligned.
In the training procedure, the software might need to configure Transceiver SI settings and Transceiver
lane rate.
8.5 Video Stream Receiver
After training is completed, DisplayPort Rx IP should enable the video stream receiver. To enable the
video receiver, the software should do the following configuration:
1. Write 0x01 into register 0x0014 to enable descrambler.
2. Write 0x01 into register 0x0010 to enable video stream receiver.
3. Reading MSA from register 0x0048 to register 0x006C until getting meaningfully MSA values.
4. Write FrameLinesNumber into register 0x00C0. Write LinePixelsNumber into register 0x00D8. For
example, we know it is 1920x1080 video stream from MSA, then write 1080 into register 0x00C0
and write 1920 into register 0x00D8.
5. Read register 0x01D4 to check if the recovered video stream frame has expected HWidth and
expected VHeight.
6. Read register 0x01F0 to clear and discard the reading value since this register records the status
from the last reading.
7. Waiting for about 1 second or several seconds, Read register 0x01F0 again. Checking bit [5] to
check if the recovered video stream HWidth is locked. 1 means unlocked and 0 means locked.
Checking bit [21] to check if recovered the video stream VHeight is locked. 1 means unlocked and 0
means locked.
8.6 Register Definition
The following table shows the internal registers defined in DisplayPort Rx IP.
Table 7 • DisplayPort Rx IP Registers
Address Bits Name Type Default Description
0x0000 [2:0] Enabled_Lanes_Number RW 0x4 Enabled lanes number 4 lanes, 2 lanes, or 1
lane
0x0004 [2:0] Out_Parallel_Pixel_Number RW 0x4 The number of parallel pixels at video
stream output interface
0x0010 [0] Video_Stream_Enable RW 0x0 Enable video stream receiver
0x0014 [0] Descramble_Enable RW 0x0 Enable descrambler
0x0018 [0] InterLane_Alignment_Status RO 0x0 Indicates if lanes are aligned
0x001C [1] Alignment_Error RC 0x0 Indicates if there is error in alignment
procedure
[0] New_Alignement RC 0x0 Indicates if there was a new alignment
event. When lanes are not aligned, a new
alignment is expected. When lanes are
aligned and there was a new alignment, it
means lanes are out of alignment and
aligned again.