User Guide

DisplayPort Rx IP Configuration
Microsemi Proprietary and Confidential UG0935 User Guide Revision 2.0 15
8 DisplayPort Rx IP Configuration
8.1 HPD
When the DisplayPort Sink device is ready and connected to the DisplayPort Source device, DisplayPort
Sink application software should assert the HPD signal to 1 by writing 0x01 into register 0x0140.
DisplayPort Sink application software should monitor the status of the sink device. If the sink device
needs a source device to read the DPCD registers, sink device software should send an HPD interrupt
by writing 0x01 into register 0x0144, then write 0x00 into 0x0144.
8.2 Receive AUX Request Transaction
When DisplayPort Rx IP received an AUX Request transaction and interrupt is enabled, the software
should receive the NewAuxReply event interrupt. The software should do the following steps to read the
received AUX Request transaction from DisplayPort IP:
1. Read register 0x012C to know the length (RequestBytesNum) of the received AUX transaction.
2. Read register 0x0124 RequestBytesNum times to get all the bytes of the received AUX transaction.
3. AUX Request transaction COMM[3:0] is the first reading byte bit [7:4].
4. DPCD address is ((FirstByte[3:0]<<16) | (SecondByte[7:0]<<8) | (ThirdByte[7:0])).
5. AUX Request Length field is FourthByte[7:0].
6. For DPCD writing Request transaction, all the bytes after the length field are writing data.
8.3 Transmit AUX Reply Transaction
After received an AUX Request transaction, the software should configure DisplayPort Rx IP to transmit
an AUX Reply transaction as soon as possible. The software is responsible to determine all the Reply
transaction bytes, which includs the Reply type.
To transmit an AUX Reply, software should do the following steps:
1. If AUX Reply transaction including DPCD reading data, write all the read data into register 0x010C
byte by byte. If no DPCD reading data to be transmitted, skip this step.
2. Determine how many DPCD reading bytes (AuxReadBytesNum). If no DPCD reading bytes,
AuxReadBytesNum is 0.
3. Determine the AUX Reply type (ReplyComm).
4. Write ((AuxReadBytesNum<<16) | ReplyComm) into register 0x0100.
8.4 DisplayPort Lanes Training
At the first training stage, the DisplayPort Source device transmits TPS1 to make the attached
DisplayPort Sink device to get LANEx_CR_DONE.
At the second training stage, the DisplayPort Source device transmits TPS2/TPS3/TPS4 to get the
attached DisplayPort Sink device to get LANEx_EQ_DONE, LANEx_SYMBOL_LOCKED, and
INTERLANE_ALIGN_DONE.
This LANEx_CR_DONE means FPGA Transceiver CDR is locked. Since, FPGA Transceiver is not part
of DisplayPort Rx IP, LANEx_CR_DONE.
LANEx_SYMBOL_LOCKED means 8B10B decoder decodes 8B bytes correctly. Since the 8B10B
decoder is not part of DisplayPort Rx IP, LANEx_SYMBOL_LOCKED.
Before the training procedure, DisplayPort Sink application software should let the source device know
that DisplayPort Rx IP supports TPS3 and TPS4.