User Guide

DisplayPort Tx IP Configuration
Microsemi Proprietary and Confidential UG0935 User Guide Revision 2.0 13
0x00D8 [15] MSA_HSync_Polarity RW 0x0 MSA_HSync_Polarity
[14:0] MSA_HSync_Width RW 0x0 MSA_HSync_Width
0x00DC [15] MSA_VSync_Polarity RW 0x0 MSA_VSync_Polarity
[14:0] MSA_VSync_Width RW 0x0 MSA_VSync_Width
0x00E0 [7:1] MSA_MISC0_ColorIndicator RW 0x0 MSA_MISC0_ColorimetryIndicator
[0] MSA_MISC0_SyncClock RW 0x0 MSA_MISC0_SynchronousClock
0x00E4 [7:6] MSA_MISC1_ColorIndicator RW 0x0 MSA_MISC1_ColorimetryIndicator
[5:3] MSA_MISC1_Reserved RW 0x0 MSA_MISC1_Reserved
[2:1] MSA_MISC1_Stero RW 0x0 MSA_MISC1_SteroVideoAttributor
[0] MSA_MISC1_InterlaceEven RW 0x0 MSA_MISC1_InterlacedVerticalTotalEven
0x00E8 [15:0] MSA_HWidth RW 0x0 MSA_HWidth
0x00EC [15:0] MSA_VHeigth RW 0x0 MSA_VHeigth
0x0100 [23:16] AUX_Tx_Data_Byte_Num RW 0x0 The number of bytes to be transmitted in this
AUX request transaction
[8] AUX_Tx_LengthField_Val RW 0x0 1 means this AUX transaction transmission
carries length field.
0 means this AUX transaction does not have
length filed.
[3:0] AUX_Tx_Command RW 0x0 AUX COMM[3:0] in this AUX transaction
transmission
0x0104 [19:0] AUX_Tx_DPCD_Address RW 0x0 DPCD address in this AUX transaction
transmission
0x0108 [7:0] AUX_Tx_Length RW 0x0 Length field in this AUX transaction
transmission. It will no ignored if no Length
field.
0x010C [7:0] AUX_Tx_Writting_Data RW 0x0 For AUX Writing Request transaction, writing
all the DPCD writing bytes into this register
byte by byte.
0x0110 [18:0] AUX_Reply_Timeout_Th RW 0x00100
0
Waiting AUX Reply timeout threshold in
aux_clk_i cycles
0x011C [15:0] AUX_TX_ Request_Num RC 0x0 The number of AUX transactions to be
transmitted
0x0120 [15:0] AUX_RX_Reply_Num RC 0x0 The number of AUX transactions to be
received
0x0150 [15:0] HPD_Status RO 0x0 The status of input HPD signal
0x0154 [0] HPD_IRQ RC 0x0 Indicates if there is HPD interrupt
0x0180 [0] IntMask_TotalInt RW 0x1 Total interrupt mask. 1 means enable total
interrupt and int_o
0x184 [5] IntMask_HPD_Disconnect RW 0x1 Interrupt mask for HPD disconnect event. 1
enable interrupt
[4] IntMask_HPD_Connect RW 0x1 Interrupt mask for HPD connect event. 1
enable interrupt
Table 6 • DisplayPort Tx IP Registers (continued)
Address Bits Name Type Default Description