User Guide

DisplayPort Tx IP Configuration
Microsemi Proprietary and Confidential UG0935 User Guide Revision 2.0 12
7.4 DisplayPort Lanes Training
At the first training stage, DisplayPort Tx IP should output TPS1 to get the attached DisplayPort Sink
device to get LANEx_CR_DONE. The software should configure the following steps to enable TPS1
transmission:
1. Write enabled lane number into register 0x0004, it could be enabled 4 lanes, 2 lanes, or 1 lane.
2. Write 0x01 into register 0x0018 to enable TPS1.
3. Write 0x00 into register 0x0010 to disable scrambler.
At second training stage, according to the DisplayPort Sink device feature, DisplayPort Tx IP should
output TPS2/TPS3/TPS4 to get the attached DisplayPort Sink device to get LANEx_EQ_DONE,
LANEx_SYMBOL_LOCKED, and INTERLANE_ALIGN_DONE. The software should configure the
following steps to enable TPS2/TPS3/TPS4 transmissions:
1. Write enabled lane number into register 0x0004. It could be enabled 4 lanes, 2 lanes, or 1 lane.
2. To transmit TPS2, write 0x02 into register 0x0018 to enable TPS2. For TPS3, writing 0x03. For
TPS4, writing 0x04.
3. For TPS2 and TPS3, write 0x00 into register 0x0010 to disable scrambler. For TPS4, write 0x01 to
enable scrambler.
In the training procedure, before sending the TPS pattern, DisplayPort Source application software might
need to configure Transceiver SI settings and the Transceiver rate. The Transceiver is not part of this IP,
and the Transceiver settings configuration guide is not included in this user guide.
7.5 Video Stream Transmission
After training is completed, DisplayPort Tx IP can transmit the video stream to the sink device. To enable
video transmission, software should do the following configuration:
1. Enable scrambler, write 0x01 into register 0x0010.
2. Configure MSA, configure registers from address 0x00C0 to address 0x00EC.
3. Enable video transmission, write 0x01 into register 0x0000.
7.6 Register Definition
The following table shows the internal registers defined in DisplayPort Tx IP.
Table 6 • DisplayPort Tx IP Registers
Address Bits Name Type Default Description
0x0000 [0] video_stream_enable RW 0x0 Enable video stream transmission
0x0008 [2:0] lane_number RW 0x4 DisplayPort enabled lane number: 4, 2, or 1
0x0010 [0] scrambler_enable RW 0x0 Enable scrambler
0x0014 [0] Interlane_skew_enable RW 0x1 Enable Inter lane skew
0x0018 [2:0] training_pattern_mode RW 0x0 Training pattern type:
0: None, 1: TPS1, 2: TPS2, 3: TPS,. and 4:
TPS4.
0x001C [0] enhanced_BS_enable RW 0x0 Enable Enhanced BS transmission
0x00C0 [23:0] MSA_Mvid RW 0x0 MSA Mvid for synchronous video clock
mode
0x00C4 [23:0] MSA_Nvid RW 0x0 MSA Nvid
0x00C8 [15:0] MSA_HTotal RW 0x0 MSA HTotal
0x00CC [15:0] MSA_VTotal RW 0x0 MSA_VTotal
0x00D0 [15:0] MSA_HStart RW 0x0 MSA HStart
0x00D4 [15:0] MSA_VStart RW 0x0 MSA_VStart