User Guide

DisplayPort Rx IP Interface Signal
Microsemi Proprietary and Confidential UG0935 User Guide Revision 2.0 10
6.2 Configuration Parameters
The configuration parameter for DisplayPort Rx IP is listed in the following table.
6.3 Key Interface Description
6.3.1 Output Video Stream Interface Signal
The following figure shows the timing diagram of the output video stream signal interface.
Figure 6 • Timing Diagram for Output Video Stream Interface Signal
As shown in the preceding figure, hsync_o is asserted for several cycles before each line. If there are n
lines in a video frame, there are n hsync_o asserted. Before the first line and the first asserted hsync_o,
vsync_o is asserted for several cycles. The position and width of VSYNC and HSYNC are configured by
software.
dp_lane_k_i 16 Input DisplayPort input lanes' data K indication. It is synchronous with dpclk_i.
Bit[15:12] for Lane0, bit[11:8] for Lane1, bit[7:4] for Lane2, and bit[3:0]
for Lane3.
dp_lane_data_i 128 Input DisplayPort input lanes' data. It is synchronous with dpclk_i.
Bit[127:96] for Lane0, bit[95:64] for Lane1, bit[63:32] for Lane2, bit[31:0]
for Lane3.
mvid_val_o 1 Output Indicates if mvid_o and nvid_o is available It is synchronous with dpclk_i.
mvid_o 24 Output Mvid, it is synchronous with dpclk_i.
nvid_o 24 Output Nvid, it is synchronous with dpclk_i.
Table 5 • Configuration parameters for DisplayPort Rx IP
Name Default Description
g_MAX_OUT_PIXEL 4 Max output parallel pixels
g_LINE_BUFFER_DEPTH 2048 Output line buffer depth. It should be greater than line pixel number.
Table 4 • DisplayPort Rx IP Interface signals (continued)
Interface Width Direction Description
4'b0000 4'b1111 4'b11114'b0000 4'b0000 4'b1111 4'b1111 4'b0000
Line0 Pixels
Line1 Pixels Line2 Pixels Last Line Pixels
Line0 Pixels
pixel_data
pixel_val
hsync
vsync
4'b1111