User Guide

DisplayPort Tx IP Interface Signal
Microsemi Proprietary and Confidential UG0935 User Guide Revision 2.0 8
5.2 Configuration Parameters
The configuration parameter for CoaXPress Host IP is listed in the following table.
5.3 Key Interface Description
5.3.1 Input Video Stream Interface Signal
The following figure shows the timing diagram of the input video stream signal interface.
Figure 5 • Timing Diagram for Input Video Stream Interface Signal
As shown in the preceding figure, hsync_i is asserted for several cycles before each line. If there are n
lines in a video frame, there are n hsync_i asserted. Before the first line and the first asserted hsync_i,
vsync_i should be asserted for several cycles.
For four parallel pixels input case, pixel_val_i should be 4'b1111 when input pixel data is available and
4'b0000 when input pixel data is not available. For two parallel pixels input case, pixel_val_i should be
2'b11 when input pixel data is available and 2'b00 when pixel data is not available. For the one pixel input
case, pixel_val_i should be 1'b1 when input pixel data is available and 1'b0 when pixel data is not
available.
aux_tx_en_o 1 Output AUX Tx data enable signal
aux_tx_io_o 1 Output AUX Tx data
aux_rx_io_i 1 Input AUX Rx data
dp_lane_k_o 16 Output DisplayPort output lanes' data K indication. It is synchronous
with dpclk_i.
Bit[15:12] for Lane0, bit[11:8] for Lane1, bit[7:4] for Lane2, and
bit[3:0] for Lane3.
dp_lane_data_o 128 Output DisplayPort output lanes' data. It is synchronous with dpclk_i.
Bit[127:96] for Lane0, bit[95:64] for Lane1, bit[63:32] for Lane2,
and bit[31:0] for Lane3.
Table 3 • Configuration parameters for CoaXPress Host IP
Name Default Description
g_IN_PIXEL_NUM 4 It defines the parallel pixel number on input video stream port.
Table 2 • DisplayPort Tx IP Interface signals (continued)
Interface Width Direction Description
4'b0000 4'b1111 4'b11114'b0000 4'b0000 4'b1111 4'b1111 4'b0000
Line0 Pixels
Line1 Pixels
Line2 Pixels
Last Line Pixels
Line0 Pixels
pixel_data
pixel_val
hsync
vsync