User Guide

Introduction
Microsemi Proprietary and Confidential UG0935 User Guide Revision 2.0 4
2.6 DisplayPort Rx IP Architecture
The following figure shows the DisplayPort Rx IP implementation.
Figure 2 • DisplayPort Rx IP Implementation
DisplayPort Rx IP includes the Descrambler module, Lane receiver module, Video Stream Receiver
module, and AUX_CH module. Descrambler de-scrambles the input lane data. Lane receiver
demultiplexes all kinds of data on each lane. The Video Stream Receiver gets video pixels from the lane
receiver, it recovers the video stream signal. AUX_CH module receives the AUX Request command from
DisplayPort Source device and transmits AUX Reply to DisplayPort Source device.
2.7 Resource Utilization
The following table lists the resource utilization of PolarFire FPGA family in DisplayPort IP (configured for
24 bits per pixel and four parallel pixels on the interface).
Table 1 • DisplayPort IP Resource Utilization
DisplayPort IP LUT DFF uSRAM LSRAM
DisplayPort Tx IP 13434 9958 53 3
DisplayPort Rx IP 28840 13674 32 28
Lane
demultiplexer
Descrambler
Descrambler
Descrambler
Descrambler
Aux
receiver
Aux
transmitter
Aux
decoder
Aux
encoder
aux_io_rx
Registers
HPD Tx
Video Stream
Receiver
Lane
demultiplexer
Lane
demultiplexer
Lane
demultiplexer
Lane Receiver
Inter
lane
deskew
aux_io_tx
AUX_CH