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Microsemi SmartFusion2 FPGA Fabric DDR Controller Configuration
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Table Of Contents
Introduction
1 – Fabric External Memory DDR Controller Configurator
Memory Settings
Fabric Interface Settings
IO Drive Strength
Enable Interrupts
Fabric Clock Frequency
Memory Bandwidth
Total Bandwidth
2 – FDDR Controller Configuration
Fabric DDR Control Registers
Fabric DDR Registers Configuration
Importing DDR Configuration Files
Exporting DDR Configuration Files
Generated Data
Firmware
Fabric DDR Configuration Path
3 – Port Description
FDDR Core Ports
Interrupt Ports
APB3 Configuration Interface
DDR PHY Interface
AXI Bus Interface
AHB0 Bus Interface
AHB1 Bus Interface
A – Product Support
Customer Service
Customer Technical Support Center
Technical Support
Website
Contacting the Customer Technical Support Center
Email
My Cases
Outside the U.S.
ITAR Technical Support
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Figure
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FDDR Configuration - Memo
ry Initialization Tab
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