User Guide

5
Fabric Interface Settings
FPGA Fabric Interface - This is the data interface between the FDDR and the FPGA design. Because
the FDDR is a memory controller, it is intended to be a slave on an AXI or AHB bus. The Master of the
bus initiates bus transactions, which are in turn interpreted by the FDDR as memory transactions and
communicated to the off-chip DDR Memory. FDDR fabric interface options are:
Using an AXI-64 Interface - One master accesses the FDDR through a 64-bit AXI interface.
Using a Single AHB-32 Interface - One master accesses the FDDR through a single 32-bit AHB
interface.
Using Two AHB-32 Interfaces - Two masters access the FDDR using two 32-bit AHB interfaces.
FPGA CLOCK Divisor - Specifies the frequency ratio between the DDR Controller clock (CLK_FDDR)
and the clock controlling the fabric interface (CLK_FIC64). The CLK_FIC64 frequency should be equal to
that of the AHB/AXI subsystem that is connected to the FDDR AHB/AXI bus interface. For example, if
you have a DDR RAM running at 200 MHz and your Fabric/AXI Subsystem runs at 100 MHz, you must
select a divisor of 2 (
Figure 1-2).
Use Fabric PLL LOCK - If CLK_BASE is sourced from a Fabric CCC, you can connect the fabric CCC
LOCK output to the FDDR FAB_PLL_LOCK input. CLK_BASE is not stable until the Fabric CCC locks.
Therefore, Microsemi recommends that you hold the FDDR in reset (i.e., assert the CORE_RESET_N
input) until CLK_BASE is stable. The LOCK output of the Fabric CCC indicates that the Fabric CCC
output clocks are stable. By checking the Use FAB_PLL_LOCK option, you can expose the
FAB_PLL_LOCK input port of the FDDR. You can then connect the LOCK output of the Fabric CCC to
the FAB_PLL_LOCK input of the FDDR.
IO Drive Strength
Select one of the following drive strengths for your DDR I/O’s:
Half Drive Strength
Full Drive Strength
Depending on your DDR Memory type and the I/O Strength you select, Libero SoC sets the DDR I/O
Standard for your FDDR system as follows:
Figure 1-2 • Fabric Interface Settings - AXI Interface and FDDR Clock Divisor Agreement
DDR Memory Type Half Drive Strength Full Drive Strength
DDR3 SSTL15I SSTL15II
DDR2 SSTL18I SSTL18II
LPDDR LPDRI LPDRII