User Guide

3
Introduction
The SmartFusion2 FPGA has two embedded DDR controllers - one accessible via the MSS (MDDR) and
the other intended for direct access from the FPGA Fabric (FDDR). The MDDR and FDDR both control
off-chip DDR memories.
To fully configure the Fabric DDR controller you must:
1. Use the Fabric External Memory DDR Controller Configurator to configure the DDR Controller,
select its datapath bus interface (AXI or AHBLite), and select the DDR clock frequency as well as
the fabric datapath clock frequency.
2. Set the register values for the DDR controller registers to match your external DDR memory
characteristics.
3. Instantiate the Fabric DDR as part of a user application and make datapath connections.
4. Connect the DDR controller's APB configuration interface as defined by the Peripheral
Initialization solution.