User Guide
Table Of Contents
16
AXI_S_CORE_RESET_N IN MDDR Global Reset
AXI_S_RMW IN Indicates whether all bytes of a 64-bit lane are valid for all beats of an
AXI transfer.
0: Indicates that all bytes in all beats are valid in the burst and the
controller should default to write commands.
1: Indicates that some bytes are invalid and the controller should
default to RMW commands.
This is classed as an AXI write address channel sideband signal and is
valid with the AWVALID signal.
Only used when ECC is enabled.
Table 3-5 • AXI Bus Interface (continued)
Port Name Direction Description