User Guide

14
DDR PHY Interface
Note: Port widths for some ports change depending on the selection of the PHY width. The notation "[a:0]/
[b:0]/[c:0]" is used to denote such ports, where "[a:0]" refers to the port width when a 32-bit PHY
width is selected, "[b:0]" corresponds to a 16-bit PHY width, and "[c:0]" corresponds to an 8-bit PHY
width.
Table 3-4 • DDR PHY Interface
Port Name Direction Description
FDDR_CAS_N OUT DRAM CASN
FDDR_CKE OUT DRAM CKE
FDDR_CLK OUT Clock, P side
FDDR_CLK_N OUT Clock, N side
FDDR_CS_N OUT DRAM CSN
FDDR_ODT OUT DRAM ODT
FDDR_RAS_N OUT DRAM RASN
FDDR_RESET_N OUT DRAM Reset for DDR3
FDDR_WE_N OUT DRAM WEN
FDDR_ADDR[15:0] OUT Dram Address bits
FDDR_BA[2:0] OUT Dram Bank Address
FDDR_DM_RDQS[4:0] INOUT Dram Data Mask
FDDR_DQS[4:0] INOUT Dram Data Strobe Input/Output - P Side
FDDR_DQS_N[4:0] INOUT Dram Data Strobe Input/Output - N Side
FDDR_DQ[35:0] INOUT DRAM Data Input/Output
FDDR_FIFO_WE_IN[2:0] IN FIFO in signal
FDDR_FIFO_WE_OUT[2:0] OUT FIFO out signal
FDDR_DM_RDQS ([3:0]/[1:0]/[0]) INOUT Dram Data Mask
FDDR_DQS ([3:0]/[1:0]/[0]) INOUT Dram Data Strobe Input/Output - P Side
FDDR_DQS_N ([3:0]/[1:0]/[0]) INOUT Dram Data Strobe Input/Output - N Side
FDDR_DQ ([31:0]/[15:0]/[7:0]) INOUT DRAM Data Input/Output
FDDR_DQS_TMATCH_0_IN IN FIFO in signal
FDDR_DQS_TMATCH_0_OUT OUT FIFO out signal
FDDR_DQS_TMATCH_1_IN IN FIFO in signal (32-bit only)
FDDR_DQS_TMATCH_1_OUT OUT FIFO out signal (32-bit only)
FDDR_DM_RDQS_ECC INOUT Dram ECC Data Mask
FDDR_DQS_ECC INOUT Dram ECC Data Strobe Input/Output - P Side
FDDR_DQS_ECC_N INOUT Dram ECC Data Strobe Input/Output - N Side
FDDR_DQ_ECC ([3:0]/[1:0]/[0]) INOUT DRAM ECC Data Input/Output
FDDR_DQS_TMATCH_ECC_IN IN ECC FIFO in signal
FDDR_DQS_TMATCH_ECC_OUT OUT ECC FIFO out signal (32-bit only)