User Guide

13
3 – Port Description
FDDR Core Ports
Interrupt Ports
This group of ports is exposed when you select the Enable Interrupts option.
APB3 Configuration Interface
Table 3-1 • FDDR Core Ports
Port Name Direction Description
CORE_RESET_N IN FDDR Controller Reset
CLK_BASE IN FDDR Fabric Interface Clock
FPLL_LOCK OUT FDDR PLL Lock output - high when FDDR PLL is locked
CLK_BASE_PLL_LOCK IN Fabric PLL Lock Input. This input is exposed only when the Use
FAB_PLL_LOCK option is selected.
Table 3-2 • Interrupt Ports
Port Name Direction Description
PLL_LOCK_INT OUT Asserts when FDDR PLL locks.
PLL_LOCKLOST_INT OUT Asserts when FDDR PLL lock is lost.
ECC_INT OUT Asserts when an ECC Event occurs.
IO_CALIB_INT OUT Asserts when I/O calibration is complete.
FIC_INT OUT Asserts when there is an error in the AHB/AXI protocol on the Fabric interface.
Table 3-3 • APB3 Configuration Interface
Port Name Direction Description
APB_S_PENABLE IN Slave Enable
APB_S_PSEL IN Slave Select
APB_S_PWRITE IN Write Enable
APB_S_PADDR[10:2] IN Address
APB_S_PWDATA[15:0] IN Write Data
APB_S_PREADY OUT Slave Ready
APB_S_PSLVERR OUT Slave Error
APB_S_PRDATA[15:0] OUT Read Data
APB_S_PRESET_N IN Slave Reset
APB_S_PCLK IN Clock