User Guide

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Note: If you are using System Builder the configuration path is set and connected automatically.
To configure the FIC_2 interface:
1. Open the FIC_2 configurator dialog (
Figure 2-5) from the MSS configurator.
2. Select the Initialize peripherals using Cortex-M3 option.
3. Make sure that the MSS DDR is checked, as are the Fabric DDR/SERDES blocks if you are using
them.
4. Click OK to save your settings. This exposes the FIC_2 configuration ports (Clock, Reset, and
APB bus interfaces), as shown in
Figure 2-6.
5. Generate the MSS. The FIC_2 ports (FIC_2_APB_MASTER, FIC_2_APB_M_PCLK and
FIC_2_APB_M_RESET_N) are now exposed at the MSS interface and can be connected to
CoreSF2Config and CoreSF2Reset as per the Peripheral Initialization solution specification.
For details on configuring and connecting the CoreSF2Config and CoreSF2Reset cores, refer to the
Peripheral Initialization Configuration Guide.
Figure 2-5FIC_2 Configurator Overview
Figure 2-6FIC_2 Ports