User Guide
Table Of Contents
3
Introduction
The FIFO Controller without Memory generates only the FIFO controller logic. This core is intended to be
used along with either a Two-Port Large SRAM or a Micro SRAM.
The FIFO Controller without Memory is independent of depth and width cascading of RAM Blocks.
The FIFO Controller without Memory has single-RAM-location granularity with the empty / full flags.
It supports many more optional status ports for increased visibility and usability. These optional ports are
described in more detail in the sections below.
In this document, we describe how you can configure a FIFO Controller without Memory instance and
define how the signals are connected.
Figure 1 • FIFO Controller without Memory Configurator