User Guide

9
Step 2: Create the FPGA Fabric DDR_FIC Sub-System
Based on the FPGA bus connection type you selected - AXI, Single AHBLite or Two AHBLite - you must
create a sub-system that matches your selection.
DDR_FIC/AXI Sub-System
1. Instantiate and configure the CoreAXI IP core from the Catalog window. Enable the slots you plan
to use for your application as well as the amount of memory per slot that matches your design
requirements. Since you are addressing an external DDR memory, your slot size selection should
match the space that you plan on addressing from the FPGA fabric master. (
Figure 3-2).
2. Instantiate and configure the AMBA AXI-compliant master core or component that is intended to
master to the AXI bus. If your application requires more than one master onto the CoreAXI bus,
instantiate the second master as well.
3. Connect the sub-system:
Connect the CoreAXI mirrored-master Bus Interface (BIF) port M0 (M1) to the master BIF port
of your master core instance(s) (
Figure 3-3).
Connect the MSS DDR_FIC slave BIF port - MDDR_DDR_AXI_SLAVE - to the proper
CoreAXI bus mirrored-slave slot as per your memory map requirement. If you have other
slaves on that bus, connect them also, as per you memory map.
Figure 3-2 • CoreAXI Configuration