User Guide

8
3 – Configuring the DDR_FIC Sub-System
To configure/create a DDR_FIC sub-system, you must:
1. Configure the MSS MDDR to expose the DDR_FIC interface
2. Create the FPGA fabric DDR_FIC sub-system including instantiation/configuration/connectivity
for:
AXI or AHBLite bus
AXI or AHBLite bus master(s)
Other masters and peripherals on the bus as required by your application
Clocks and resets; refer to
"Configuring the FIC Sub-System Clocks" on page 23 and
"Configuring the FIC Sub-System Reset" on page 27
These steps are described in detail below.
Step 1: Configure the MSS MDDR Sub-block to Expose the
DDR_FIC Bus Interface
The DDR_FIC interface is exposed when your application needs to access the external DDR memory
from the FPGA fabric. In this configuration, the MDDR sub-block exposes the DDR_FIC interface, which
is a slave AXI or AHBLite Bus Interface (BIF) (
Figure 3-1).
Figure 3-1 • MSS DDR Configuration with Access from FPGA Fabric