User Guide

3
Introduction
The SmartFusion2 Microcontroller Sub-System (MSS) offers four different Fabric Interface Controllers
(FIC):
DDR_FIC
•SMC_FIC
FIC_0 and FIC_1, depending on your device
These interface blocks enable the MSS to interface with logic implemented in the FPGA fabric and vice
versa.
The DDR_FIC is used when you configure the MSS DDR block (MDDR) such that the external DDR
memory can be accessed from an FPGA fabric master via an AXI interface or 2 AHBLite AMBA
interfaces.
The SMC_FIC is used when you configure the MSS DDR Block in the Single Date Rate (SDR) mode. In
this configuration, the MSS accesses external Single Data Rate DRAM or Asynchronous memories via a
soft memory controller instantiated in the FPGA fabric, such as CoreSDR_AXI. The SMC_FIC is an AXI
or AHBLite slave AMBA interface. The DDR_FIC and SMC_FIC interfaces are mutually exclusive; only
one is active at a time.
The FIC interfaces enable you to naturally extend the MSS AMBA Bus into the FPGA fabric. There are
up to two FIC instances per MSS depending on the selected device. The first instance is named FIC_0
(which is available on every device) and the second is named FIC_1 (may not be present in the smaller
devices). You can configure the FIC as either an APB3 or AHBLite AMBA interface depending on your
design needs. In each mode, a master and a slave bus interface is available. That is, a master in the
fabric can interface to a slave in the MSS and a master in the MSS can interface to a slave in the fabric.
Each Fabric Interface sub-system can operate on a different clock frequency, defined as a ratio of the
MSS main clock M3_CLK.
The SmartFusion2 architecture imposes rules related to clocking domains between the Fabric Interfaces
and the FPGA Fabric. This document provides guidance on how to properly construct such systems.
High-Level View
Figure 1
and Figure 2 show how the MSS connects to the FPGA fabric via the various Fabric Interface
Controllers (FIC).
Figure 1 shows an overall block diagram when DDR_FIC is used (external DDR
memory) and
Figure 2 shows a block diagram for when SMC_FIC is used (external SDR memory).
The diagrams show the MSS sub-blocks essential to connecting the MSS to the FPGA fabric. The FIC
sub-block may or not be used in your application
. You also may not be using the DDR_FIC or SMC_FIC