User Guide
Table Of Contents
- Introduction
- 1 – MSS Configurator
- 2 – SmartDesign and MSS Configurator Actions
- 3 – Configuring the DDR_FIC Sub-System
- 4 – Configuring the SMC_FIC Sub-System
- 5 – Configuring the FIC Sub-Systems
- 6 – Configuring the FIC Sub-System Clocks
- 7 – Configuring the FIC Sub-System Reset
- 8 – Configuring the System Memory Map
- A – Product Support
25
Note: If two FIC sub-systems have the same frequencies, you do not need to generate two independent
global outputs from the fabric CCC; one is sufficient.
Step 3: Connect the FPGA Fabric FIC Sub-Systems Clock
Networks
Connect each fabric CCC global output GLx to the FIC sub-system it is associated with.
Step 4: Connect the MSS CLK_BASE Port
Connect the slowest of the fabric CCC global output GLx to the MSS CLK_BASE port.
Step 5: Connect the MSS MCCC_CLK_BASE_PLL_LOCK Port
Connect the fabric CCC LOCK output to the MSS MCCC_CLK_BASE_PLL_LOCK port.
Figure 6-3 • Fabric CCC with PLL