User Guide

23
6 – Configuring the FIC Sub-System Clocks
To create the proper clock configuration and connectivity, you must:
Configure the MSS CCC FIC clocks
Instantiate and configure an FPGA fabric CCC core
Connect the clock networks for each FIC sub-system
Connect the MSS CLK_BASE port to the correct FPGA fabric FIC sub-system clock network
The SmartFusion2 architecture imposes a number of rules that must be followed for all FIC sub-systems
to interact properly between the MSS logic and FPGA fabric logic. These rules are defined below and
shown in
Figure 6-1.
1. Each FPGA fabric FIC sub-system must be driven by a clock whose clock frequency matches the
frequency defined, for that particular sub-system, in the MSS CCC configurator.
2. All FPGA fabric FIC sub-system clocks must be precisely aligned; the clocks may be of different
frequencies, but the rising edges of the slower clocks must be aligned to the rising edges of the
fastest clocks.
3. The FPGA fabric FIC sub-system clock with the smallest frequency must drive the MSS
CLK_BASE.
4. If the fabric clocks are derived from a fabric CCC (with PLL), the fabric CCC LOCK output must be
connected to the MSS_CCC_CLK_BASE_PLL_LOCK port. The MSS CCC Fabric Alignment
Clock Circuitry (FACC) monitors the CLK_BASE PLL LOCK signal to guarantee that CLK_BASE
is stable before switching from the standby clock (clock used during device boot up) to the user-
configured clock derived from CLK_BASE.
Follow the steps below to configure the clock networks for all your FIC sub-systems.
Figure 6-1 • Sub-System Clock Rules