User Guide
Table Of Contents
- Introduction
- 1 – MSS Configurator
- 2 – SmartDesign and MSS Configurator Actions
- 3 – Configuring the DDR_FIC Sub-System
- 4 – Configuring the SMC_FIC Sub-System
- 5 – Configuring the FIC Sub-Systems
- 6 – Configuring the FIC Sub-System Clocks
- 7 – Configuring the FIC Sub-System Reset
- 8 – Configuring the System Memory Map
- A – Product Support
17
5 – Configuring the FIC Sub-Systems
To configure/create a FIC sub-system, you must:
1. Configure the MSS FIC to expose the FIC interface
2. Create the FPGA fabric FIC sub-system including instantiation/configuration/connectivity for:
– APB3 or AHBLite bus
– APB3 and AHBLite compliant master and/or peripherals configuration and connection onto
the bus as required by your application
– Clocks and resets; refer to
"Configuring the FIC Sub-System Clocks" on page 23 and
"Configuring the FIC Sub-System Reset" on page 27
These steps are described in detail below.
Step 1: Configure the MSS FIC Sub-Block
1. Invoke the FIC Configurator and right-click on FIC_0 or FIC_1 to open the FIC Configurator.
2. In the Configurator for the MSS to FPGA Fabric Interface configuration group select:
– The AHBLite or APB3 interface type
– Whether you intend to use the interface as a master of the FPGA fabric
– Whether you intend to use the interface as a slave mastered by the FPGA fabric (
Figure 5-1)
3. If you are using an AHBLite Interface you can also use the Advanced AHBLite Options to select
the bypass mode, or expose the master ID port if you selected the interface to act as a master of
the fabric (
Figure 5-2).
Figure 5-1 • MSS to FPGA Fabric Interface Options
Figure 5-2 • Advanced AHBLite Options