User Guide

15
Step 2: Create the FPGA Fabric SMC_FIC Sub-System
1. Instantiate and configure the CoreAXI such that the master slot M0 is enabled for the slave slot
S0, as shown in
Figure 4-2. Since you are addressing an external memory via a soft memory
controller, your slot size selection should match the amount of external memory space that you
plan on addressing from the Cortex-M3 processor or any master writing to that external memory
via the MSS DDR bridge.
2. From the IP Catalog, instantiate and configure CoreSDR_AXI to match your external memory
parameters.
3. Connect the sub-system (
Figure 4-3):
Connect the MSS SMC_FIC master BIF port - MDDR_SMC_AXI_MASTER - to the CoreAXI
bus mirrored-master M0.
Connect the CoreAXI mirrored-slave Bus Interface (BIF) port S0 to the slave BIF port of the
CoreSDR_AXI core instance.
Figure 4-2 • CoreAXI Configuration - SMC_FIC Mode