User Guide

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Clocks and resets; refer to "Configuring the FIC Sub-System Clocks" on page 23 and
"Configuring the FIC Sub-System Reset" on page 27.
DDR_FIC/Single-AHBLite sub-system
1. Instantiate and configure the CoreAHBLite IP core from the Catalog. Enable the slots that you
plan to use for your application as shown in
Figure 3-4. In this example, CoreAHBLite is
configured to address one 4GB of DDR RAM memory space using slot0 from master M0. Since
you are addressing an external DDR memory, your slot size selection should match the amount of
DDR memory space that you plan on addressing from the FPGA fabric master.
Figure 3-3 • DDR_FIC AXI Sub-System