Datasheet

MT8870D/MT8870D-1 Data Sheet
14
Zarlink Semiconductor Inc.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
*NOTES:
1. Used for guard-time calculation purposes only.
2. These, user adjustable parameters, are not device specifications. The adjustable settings of these minimums and maximums
are recommendations based upon network requirements.
3. With valid tone present at input, t
PU
equals time from PDWN going low until ESt going high.
AC Electrical Characteristics - V
DD
=5.0V±5%, V
SS
=0V, -40°C ≤ To ≤ +85°C, using Test Circuit shown in Figure 10.
Characteristics Sym. Min. Typ.
‡
Max. Units Conditions
1
T
I
M
I
N
G
Tone present detect time t
DP
51114msNote 1
2 Tone absent detect time t
DA
0.5 4 8.5 ms Note 1
3 Tone duration accept t
REC
40 ms Note 2
4 Tone duration reject t
REC
20 ms Note 2
5 Interdigit pause accept t
ID
40 ms Note 2
6 Interdigit pause reject t
DO
20 ms Note 2
7
O
U
T
P
U
T
S
Propagation delay (St to Q) t
PQ
811µsTOE=V
DD
8 Propagation delay (St to StD) t
PStD
12 16 µsTOE=V
DD
9 Output data set up (Q to StD) t
QStD
3.4 µsTOE=V
DD
10 Propagation delay (TOE to Q
ENABLE)
t
PTE
50 ns load of 10 kΩ,
50 pF
11 Propagation delay (TOE to Q
DISABLE)
t
PTD
300 ns load of 10 kΩ,
50 pF
12
P
D
W
N
Power-up time t
PU
30 ms Note 3
13 Power-down time t
PD
20 ms
14
C
L
O
C
K
Crystal/clock frequency f
C
3.575
9
3.579
5
3.583
1
MHz
15 Clock input rise time t
LHCL
110 ns Ext. clock
16 Clock input fall time t
HLCL
110 ns Ext. clock
17 Clock input duty cycle DC
CL
40 50 60 % Ext. clock
18 Capacitive load (OSC2) C
LO
30 pF