User manual

(04) Get the CPU type (Beep)=1 -1-2-1.CPU register test. Programmable Interval
Timer test failure.
(05) [Beep]=1-2-2 DMA initialization in-progress or failure.
(06) Initialize system hardware (Beep)=1 -1-2-3.DMA page register write/read
test in-progress or fail.
(08) Initialize chipset registers with POST values. [Beep]= 1 -3-1 RAM refresh
verification in -progress or failure.
(09) Set POST flay.(Beep)=1-1-3-2. 1st 64K RAM test in-progress.
(0A) Initialize CPU registers. (Beep)=1 -1-3-3. Perform BIOS checksum test. 1st
64K RAM chip or data line failure multi -bit.
(0B)Enable CPU Cable -Check CPU Jumpers. [Beep]=1 -3-4 1st 64K RAM odd/even
logic failure.
(0C) Initialize cache to initial POST value. Test DMA page registers. [Beep]=1 -4-1
1st 64K RAM address line failure.
(0D) [Beep]=1-4-2 1st 64K RAM parity test in progress or failure.
(0E) Initialize I/O.(Beep)=1 -1-4-3. Test 8254 timers.
(0F) Initialize the local IDE
10) Initialize Power Management.(Beep)=1 -2-1-1.Initialize 8254 timers.[Beep]=2
-1-1 1st 64K RAM chip or data line failure-bit 0.
(11) Load alternate registers with POST values.(Beep)=1 -2- 2. 1st 64K RAM chip
or data line failure-bit 1.
(12) Restore CPU control word during warm boot. J ump to User Path
0.(Beep)=1-2-1-3.Test both 8237 DMA controllers. 1st 64K RAM chip or data line
failure-bit 2.
(13)[Beep]=2 -1-4 1st 64K RAM chip or data line failure -bit 3. Initialize PCI Bus
Mastering devices.
(14) Initialize keyboard controller.(Beep)=1 -2-2-1.Initialize 823 7 DMA
controllers.[Beep]=2 -2-1 1st 64K RAM chip or data line failure -bit 4.
(15) [Beep]=2-2-2 1st 64K RAM chip or data line failure-bit 5.
(16) BIOS ROM checksum .(Beep)=1 -2-2-3. Initialize 8259, reset
Coprocessor.[Beep]=2 -2-3 1st 64K RAM chip or data line failure -bit 6.
(17)Initialize cache before memory auto -size.[Beep] =2-2-4 1st 64K RAM chip or
data line failure-bit 7.
(18)8254 timer initialization.(Beep)=1 -2-3-1. Test 8259 interrupt controllers
registers.[Beep]=2-3-1 1st 64K RAM chip or data line failure -bit 8.
(19) check memory[Beep]=2-3-2 1st 64K RAM chip or data line failure -bit 9.
(1A) 8237 DMA controller initialization.(Beep)=1 -2-3-3. Verify refresh is
occurring.[Beep]=2 -3-3 1st 64K RAM chip or data line failure-bit A.
(1B) [Beep]=2 -4-1 1st 64K RAM chip or data line failure - bit B.
(1C) [Beep]=2 -4-1 1st 64K RAM chip or data line failure- bit C. Reset
Programmable Interrupt Controller.(Beep)=1 -2 ¨C4-1.Base 64K address test.
(1D) [Beep]=2-4-2 1st 64K RAM chip or data line failure - bit D
(1E) [Beep]=2-4-3 1st 64K RAM chip or data line failure - bit E. Base 64K RAM
test(16 b its).
(1F) [Beep]=2-4-4 1st 64K RAM chip or data line failure - bi t F.
(20) [Beep]=3-1-1 master DMA register test in -progress or failure. Test DRAM
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