User manual

About to start DMA controller test.
(44) Interrupts enabled(if post switch is on). Going to initialize data to check
memory wrap around at 0:0.
(45) Data initialized. Going to check for memory wrap around at 0:0 and the total
system memory size.
(46) Memory wrap around test done. Memory size calculation over, writing pat
terns to test memory.
(47)Pattern to be tested written in extended memory, 640 K memory.
(48)Patterns written in base memory. Going to find out amount of memory below
1M memory.
(49)Memory below 1M found and verified. Going to find out amount of memory
above 1M memory.
(4A)Amount of memory above 1M found and verified. Going for BIOS ROM data
area check.
(4B) Amount o f memory above 1M found and verified. Check for soft reset and
going to clear memory below 1M for reset (If power on, go to check point#4Eh).
BIOS ROM data area check over. Going to check <ESC> and to clear memory
below 1M for soft reset.
(4C) Memory below 1M cleared. (SOFT RESET) Going to clear memory above 1M.
(4D) Memory above 1M cleared. (SOFT RESET)Going to save the memory size.
(GOTO check point#52h).
(4E) Memory test started. (NO SOFT RESET) About to display the first 64K
memory test.
(4F) Memory size display started. This will be updated during memory test. Going
for sequential and random memory test. Processor in real mode after shutdown.
(50) Memory testing/initialization below 1M complete. Going to adjust displayed
memory size for relocation /shadow. DMA page register test complete.
(51) Memory size display adjusted due to relocation /shadow. Memory test above
1M to follow. DMA unit -1 base register test about to start.
(52) Memory testing/initialization below 1M complete. Going to save memory size
information. Going to prepare to go back to real mode. DMA un it-1 channel OK,
about to begin CH-2.
(53) Memory size information is saved. CPU registers are saved. Going to enter in
real mode. DMA CH-2 base register test OK.
(54) Shutdown successful, CPU in real mode. Going to restore registers saved
during preparation for shut down. About to check F/F latch for unit-1 and unit-2.
(55) Registers restored. Going to disable gate A20 address line. F/F latch for both
units checked.
(56) A20 address line disable successful. BIOS ROM data area about to be checked.
DMA unit 1 and 2 programming over and about to initialize 8259 interrupt
controller.
(57) A20 address line disable successful. BIOS ROM data area check halfway. BIOS
ROM data area check to be com plete.8259 initialization over.
(58) Memory size adjusted for relocation/shadow. Going to clear Hit<DEL>
message. BIOS ROM data area check over. Going to clear Hit<ESC > message.
8259 mask register check OK.
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