Datasheet

USB3320
DS00001792E-page 8  2014-2016 Microchip Technology Inc.
22 VBUS
I/O,
Analog
N/A This pin connects to an external resistor
(R
VBUS
) connected to the VBUS pin of the
USB cable. This pin is used for the VBUS
comparator inputs and for VBUS pulsing
during session request protocol. See
Table 5-7, "Required RVBUS Resistor
Value".
23 ID
Input,
Analog
N/A ID pin of the USB cable. For applications
not using ID this pin can be connected to
VDD33. For an A-Device ID is grounded.
For a B-Device ID is floated.
24 RBIAS
Analog,
CMOS
N/A Bias Resistor pin. This pin requires an
8.06kΩ (±1%) resistor to ground, placed as
close as possible to the USB3320.
Nominal voltage during ULPI operation is
0.8V.
25 XO
Output,
CMOS
N/A External resonator pin. When using an
external clock on REFCLK, this pin should
be floated.
26 REFCLK
Input,
CMOS
N/A ULPI Output Clock Mode:
Reference frequency as defined in Table 5-
10.
ULPI Input Clock Mode:
60MHz ULPI clock input.
27 RESETB
Input,
CMOS,
Low When low, the part is suspended with all
ULPI outputs tri-stated. When high, the
USB3320 will operate as a normal ULPI
device, as described in Section 5.5.2. The
state of this pin may be changed
asynchronously to the clock signals. When
asserted for a minimum of 1 microsecond
and then de-asserted, the ULPI registers
are reset to their default state and all
internal state machines are reset.
28 VDD18
Power N/A External 1.8V Supply input pin. This pad
needs to be bypassed with a 0.1uF
capacitor to ground, placed as close as
possible to the USB3320.
29 STP
Input,
CMOS
High The Link asserts STP for one clock cycle
to stop the data stream currently on the
bus. If the Link is sending data to the
transceiver, STP indicates the last byte of
data was on the bus in the previous cycle.
30 VDD18
Power N/A External 1.8V Supply input pin. This pad
needs to be bypassed with a 0.1uF
capacitor to ground, placed as close as
possible to the USB3320.
31 DIR
Output,
CMOS
N/A Controls the direction of the data bus.
When the transceiver has data to transfer
to the Link, it drives DIR high to take
ownership of the bus. When the
transceiver has no data to transfer it drives
DIR low and monitors the bus for
commands from the Link.
32 VDDIO
Power N/A External 1.8V to 3.3V ULPI supply input
pin. This voltage sets the value of V
OH
for
the ULPI signals. This pad needs to be
bypassed with a 0.1uF capacitor to ground,
placed as close as possible to the
USB3320.
FLAG GND
Ground N/A Ground.
TABLE 2-1: USB3320 PIN DESCRIPTION (CONTINUED)
Pin Name
Direction/
Type
Active
Level
Description