Datasheet
Table Of Contents
- 1.0 Introduction
- 2.0 USB3320 Pin Locations and Definitions
- 3.0 Limiting Values
- 4.0 Electrical Characteristics
- 4.1 Operating Current
- 4.2 Clock Specifications
- 4.3 ULPI Interface Timing
- 4.4 Digital IO Pins
- 4.5 DC Characteristics: Analog I/O Pins
- 4.6 Dynamic Characteristics: Analog I/O Pins
- 4.7 OTG Electrical Characteristics
- 4.8 USB Audio Switch Characteristics
- 4.9 Regulator Output Voltages and Capacitor Requirement
- 4.10 Piezoelectric Resonator for Internal Oscillator
- 5.0 Architecture Overview
- FIGURE 5-1: USB3320 Internal Block Diagram
- 5.1 ULPI Digital Operation and Interface
- 5.2 USB 2.0 Hi-Speed Transceiver
- 5.3 Bias Generator
- 5.4 Integrated Low Jitter PLL
- 5.5 Internal Regulators and POR
- 5.6 USB On-The-Go (OTG)
- 5.7 USB UART Support
- 5.8 USB Charger Detection Support
- 5.9 USB Audio Support
- 5.10 Reference Frequency Selection
- 6.0 ULPI Operation
- 6.1 Overview
- 6.2 ULPI Register Access
- 6.3 Low Power Mode
- 6.4 Full Speed/Low Speed Serial Modes
- 6.5 Carkit Mode
- 6.6 RID Converter Operation
- 6.7 Headset Audio Mode
- 7.0 ULPI Register Map
- 8.0 Application Notes
- 8.1 Application Diagram
- TABLE 8-1: Component Values in Application Diagrams
- TABLE 8-2: Capacitance Values at VBUS of USB Connector
- FIGURE 8-1: USB3320 Application Diagram (Device, ULPI Output Clock mode, 24MHz)
- FIGURE 8-2: USB3320 Application Diagram (Device, ULPI Input Clock mode, 60MHz)
- FIGURE 8-3: USB3320 Application Diagram (Host or OTG, ULPI Output Clock Mode, 24MHz)
- 8.2 Reference Designs
- 8.3 ESD Performance
- 8.1 Application Diagram
- 9.0 Package Information
- Appendix A: Data Sheet Revision History
- The Microchip Web Site
- Customer Change Notification Service
- Customer Support
- Product Identification System
- Worldwide Sales and Service
2014-2016 Microchip Technology Inc. DS00001792E-page 61
USB3320
FIGURE 8-3: USB3320 APPLICATION DIAGRAM (HOST OR OTG, ULPI OUTPUT CLOCK
MODE, 24MHZ)
VBUS
Switch
OUT
EN
IN
5V
VBUS
22
VBAT
21
VDD33
20
ID
23
DM
DP
19
18
SPK_L
SPK_R
16
15
GND
Optional
Switched Signal
to DP/DM
USB
Receptacle
DM
DP
ID
SHIELD
GND
VBUS
C
OUT
3.1-5.5V
Supply
C
BYP
R
VBUS
The capacitor C
VBUS
must be installed on
this side of R
VBUS
.
C
VBUS
R
VBUS
must be
installed to enable
overvoltage
protection of the
VBUS pin.
REFSEL2
14
REFSEL1
11
REFSEL0
8
VDDIO Supply
CPEN
17
Link Controller
DIR
NXT
STP
CLKIN
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA0
DATA1
RESETB
R
BIAS
DIR
NXT
STP
CLKOUT
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA0
DATA1
13
10
9
7
6
5
4
3
29
2
31
1
RESETB
27
24
RBIAS
VDD18
28, 30
1.8V Supply
C
BYP
VDDIO
C
BYP
VDDIO Supply
32
26
25
1M
C
LOAD
Resonator
Crystal
and Caps
- or -
REFCLK
XO
For Host applications (non-OTG), the
ID pin should be connected to GND.