Datasheet
Table Of Contents
- 1.0 Introduction
- 2.0 USB3320 Pin Locations and Definitions
- 3.0 Limiting Values
- 4.0 Electrical Characteristics
- 4.1 Operating Current
- 4.2 Clock Specifications
- 4.3 ULPI Interface Timing
- 4.4 Digital IO Pins
- 4.5 DC Characteristics: Analog I/O Pins
- 4.6 Dynamic Characteristics: Analog I/O Pins
- 4.7 OTG Electrical Characteristics
- 4.8 USB Audio Switch Characteristics
- 4.9 Regulator Output Voltages and Capacitor Requirement
- 4.10 Piezoelectric Resonator for Internal Oscillator
- 5.0 Architecture Overview
- FIGURE 5-1: USB3320 Internal Block Diagram
- 5.1 ULPI Digital Operation and Interface
- 5.2 USB 2.0 Hi-Speed Transceiver
- 5.3 Bias Generator
- 5.4 Integrated Low Jitter PLL
- 5.5 Internal Regulators and POR
- 5.6 USB On-The-Go (OTG)
- 5.7 USB UART Support
- 5.8 USB Charger Detection Support
- 5.9 USB Audio Support
- 5.10 Reference Frequency Selection
- 6.0 ULPI Operation
- 6.1 Overview
- 6.2 ULPI Register Access
- 6.3 Low Power Mode
- 6.4 Full Speed/Low Speed Serial Modes
- 6.5 Carkit Mode
- 6.6 RID Converter Operation
- 6.7 Headset Audio Mode
- 7.0 ULPI Register Map
- 8.0 Application Notes
- 8.1 Application Diagram
- TABLE 8-1: Component Values in Application Diagrams
- TABLE 8-2: Capacitance Values at VBUS of USB Connector
- FIGURE 8-1: USB3320 Application Diagram (Device, ULPI Output Clock mode, 24MHz)
- FIGURE 8-2: USB3320 Application Diagram (Device, ULPI Input Clock mode, 60MHz)
- FIGURE 8-3: USB3320 Application Diagram (Host or OTG, ULPI Output Clock Mode, 24MHz)
- 8.2 Reference Designs
- 8.3 ESD Performance
- 8.1 Application Diagram
- 9.0 Package Information
- Appendix A: Data Sheet Revision History
- The Microchip Web Site
- Customer Change Notification Service
- Customer Support
- Product Identification System
- Worldwide Sales and Service
USB3320
DS00001792E-page 6 2014-2016 Microchip Technology Inc.
2.0 USB3320 PIN LOCATIONS AND DEFINITIONS
2.1 USB3320 Pin Locations and Descriptions
2.1.1 PACKAGE DIAGRAM WITH PIN LOCATIONS
The illustration below is viewed from the top of the package.
2.1.2 PIN DEFINITIONS
The following table details the pin definitions for the figure above.
FIGURE 2-1: USB3320 PIN LOCATIONS - TOP VIEW
TABLE 2-1: USB3320 PIN DESCRIPTION
Pin Name
Direction/
Type
Active
Level
Description
1CLKOUT
Output,
CMOS
N/A ULPI Output Clock Mode:
60MHz ULPI clock output. All ULPI signals
are driven synchronous to the rising edge
of this clock.
ULPI Input Clock Mode:
This pin is connected to VDDIO to
configure 60MHz ULPI Input Clock mode
as described in Section 5.4.1.
Following POR or hardware reset, the
voltage at CLKOUT must not exceed
V
IH_ED
as provided inTa bl e 4- 4.
2NXT
Output,
CMOS
High The transceiver asserts NXT to throttle the
data. When the Link is sending data to the
transceiver, NXT indicates when the
current byte has been accepted by the
transceiver. The Link places the next byte
on the data bus in the following clock
cycle.
3 DATA[0]
I/O,
CMOS
N/A
ULPI bi-directional data bus.
CLKOUT
NXT
DATA0
DATA1
DATA2
DATA3
REFSEL0
DATA4
DATA5
DATA6
REFSEL1
N/C
DATA7
REFSEL2
SPK_R
SPK_L
RBIAS
CPEN
DM
DP
VBUS
VBAT
VDD33
ID
VDDIO
XO
RESETB
REFCLK
VDD18
STP
VDD18
DIR
USB3300
Hi-Speed USB2
ULPI PHY
32 Pin QFN
1
2
3
4
5
6
7
8
Hi-Speed USB
ULPI PHY
32 Pin QFN
GND FLAG
9
10
11
12
13
14
15
16
24
23
22
21
20
19
18
17
32
31
30
29
28
27
26
25