Datasheet
Table Of Contents
- 1.0 Introduction
- 2.0 USB3320 Pin Locations and Definitions
- 3.0 Limiting Values
- 4.0 Electrical Characteristics
- 4.1 Operating Current
- 4.2 Clock Specifications
- 4.3 ULPI Interface Timing
- 4.4 Digital IO Pins
- 4.5 DC Characteristics: Analog I/O Pins
- 4.6 Dynamic Characteristics: Analog I/O Pins
- 4.7 OTG Electrical Characteristics
- 4.8 USB Audio Switch Characteristics
- 4.9 Regulator Output Voltages and Capacitor Requirement
- 4.10 Piezoelectric Resonator for Internal Oscillator
- 5.0 Architecture Overview
- FIGURE 5-1: USB3320 Internal Block Diagram
- 5.1 ULPI Digital Operation and Interface
- 5.2 USB 2.0 Hi-Speed Transceiver
- 5.3 Bias Generator
- 5.4 Integrated Low Jitter PLL
- 5.5 Internal Regulators and POR
- 5.6 USB On-The-Go (OTG)
- 5.7 USB UART Support
- 5.8 USB Charger Detection Support
- 5.9 USB Audio Support
- 5.10 Reference Frequency Selection
- 6.0 ULPI Operation
- 6.1 Overview
- 6.2 ULPI Register Access
- 6.3 Low Power Mode
- 6.4 Full Speed/Low Speed Serial Modes
- 6.5 Carkit Mode
- 6.6 RID Converter Operation
- 6.7 Headset Audio Mode
- 7.0 ULPI Register Map
- 8.0 Application Notes
- 8.1 Application Diagram
- TABLE 8-1: Component Values in Application Diagrams
- TABLE 8-2: Capacitance Values at VBUS of USB Connector
- FIGURE 8-1: USB3320 Application Diagram (Device, ULPI Output Clock mode, 24MHz)
- FIGURE 8-2: USB3320 Application Diagram (Device, ULPI Input Clock mode, 60MHz)
- FIGURE 8-3: USB3320 Application Diagram (Host or OTG, ULPI Output Clock Mode, 24MHz)
- 8.2 Reference Designs
- 8.3 ESD Performance
- 8.1 Application Diagram
- 9.0 Package Information
- Appendix A: Data Sheet Revision History
- The Microchip Web Site
- Customer Change Notification Service
- Customer Support
- Product Identification System
- Worldwide Sales and Service
USB3320
DS00001792E-page 58 2014-2016 Microchip Technology Inc.
8.0 APPLICATION NOTES
8.1 Application Diagram
The USB3320 requires few external components as shown in the application diagrams. The USB 2.0 Specification
restricts the voltage at the VBUS pin to a maximum value of 5.25V. In some applications, the voltage will exceed this
voltage, and the USB3320 provides an integrated overvoltage protection circuit. The overvoltage protection circuit works
with an external resistor (R
VBUS
) to lower the voltage at the VBUS pin, as described in Section 5.6.2.6.
Following POR or hardware reset, the voltage at CLKOUT must not exceed V
IH_ED
as provided in Table 4-4.
TABLE 8-1: COMPONENT VALUES IN APPLICATION DIAGRAMS
Reference
Designator
Value Description Notes
C
OUT
2.2F Bypass capacitor to ground (<1ESR) for
regulator stability.
Place as close as possible to the
transceiver.
C
VBUS
See Tab le 8- 2 Capacitor to ground required by the USB
Specification. Microchip recommends <1
ESR.
Place near the USB connector.
C
BYP
System
dependent.
Bypass capacitor to ground. Typical
values used are 0.1 or 0.01 F.
Place as close as possible to the
transceiver.
C
DC_LOAD
System
dependent.
The USB connector housing may be AC-
coupled to the device ground.
Industry convention is to ground
only the host side of the cable
shield.
R
VBUS
1k or 10k Series resistor to work with internal
overvoltage protection.
10k in device applications.
See Table 5 -7 for required values in Host
or OTG applications.
See Section 5.6.2.6 for information
regarding power dissipation.
R
BIAS
8.06k (±1%) Series resistor to establish reference
voltage.
See Section 5.3 for information
regarding power dissipation.
TABLE 8-2: CAPACITANCE VALUES AT VBUS OF USB CONNECTOR
Mode MIN Value MAX Value
Host 120F
Device 1F10F
OTG 1F6.5F