Datasheet
Table Of Contents
- 1.0 Introduction
- 2.0 USB3320 Pin Locations and Definitions
- 3.0 Limiting Values
- 4.0 Electrical Characteristics
- 4.1 Operating Current
- 4.2 Clock Specifications
- 4.3 ULPI Interface Timing
- 4.4 Digital IO Pins
- 4.5 DC Characteristics: Analog I/O Pins
- 4.6 Dynamic Characteristics: Analog I/O Pins
- 4.7 OTG Electrical Characteristics
- 4.8 USB Audio Switch Characteristics
- 4.9 Regulator Output Voltages and Capacitor Requirement
- 4.10 Piezoelectric Resonator for Internal Oscillator
- 5.0 Architecture Overview
- FIGURE 5-1: USB3320 Internal Block Diagram
- 5.1 ULPI Digital Operation and Interface
- 5.2 USB 2.0 Hi-Speed Transceiver
- 5.3 Bias Generator
- 5.4 Integrated Low Jitter PLL
- 5.5 Internal Regulators and POR
- 5.6 USB On-The-Go (OTG)
- 5.7 USB UART Support
- 5.8 USB Charger Detection Support
- 5.9 USB Audio Support
- 5.10 Reference Frequency Selection
- 6.0 ULPI Operation
- 6.1 Overview
- 6.2 ULPI Register Access
- 6.3 Low Power Mode
- 6.4 Full Speed/Low Speed Serial Modes
- 6.5 Carkit Mode
- 6.6 RID Converter Operation
- 6.7 Headset Audio Mode
- 7.0 ULPI Register Map
- 8.0 Application Notes
- 8.1 Application Diagram
- TABLE 8-1: Component Values in Application Diagrams
- TABLE 8-2: Capacitance Values at VBUS of USB Connector
- FIGURE 8-1: USB3320 Application Diagram (Device, ULPI Output Clock mode, 24MHz)
- FIGURE 8-2: USB3320 Application Diagram (Device, ULPI Input Clock mode, 60MHz)
- FIGURE 8-3: USB3320 Application Diagram (Host or OTG, ULPI Output Clock Mode, 24MHz)
- 8.2 Reference Designs
- 8.3 ESD Performance
- 8.1 Application Diagram
- 9.0 Package Information
- Appendix A: Data Sheet Revision History
- The Microchip Web Site
- Customer Change Notification Service
- Customer Support
- Product Identification System
- Worldwide Sales and Service
2014-2016 Microchip Technology Inc. DS00001792E-page 57
USB3320
Note 7-4 rd: Read Only with auto clear.
7.1.3.4 USB IO & Power Management
Address = 39-3Bh (read), 39h (write), 3Ah (set), 3Bh (clear)
RidIntEn 6 rd/w/s/c 0b When enabled an interrupt will be generated on the
alt_int of the RXCMD byte when RidConversionDone
bit is asserted.
Note: This register bit is or’ed with the RidIntEn bit
of the Carkit Interrupt Status register.
Reserved 7 rd 0b Read only, 0.
Field Name Bit Access Default Description
Reserved 0 rd/w/s/c 0b Read only, 0.
SwapDP/DM 1 rd/w/s/c 0b When asserted, the DP and DM pins of the USB
transceiver are swapped. This bit can be used to
prevent crossing the DP/DM traces on the board. In
UART mode, it swaps the routing to the DP and DM
pins. In USB Audio Mode, it does not affect the SPK_L
and SPK_R pins.
UART RegOutput 3:2 rd/w/s/c 01b Controls the output voltage of the VBAT to VDD33
regulator in UART mode. When the transceiver is
switched from USB mode to UART mode regulator
output will automatically change to the value specified
in this register when TxdEn is asserted.
00: 3.3V
01: 3.0V (default)
10: 2.75V
11: 2.5V
Note: When in USB Audio Mode the regulator will
remain at 3.3V. When using this register it is
recommended that the Link exit UART mode
by using the RESETB pin.
ChargerPullupEnDP 4 rd/w/s/c 0b Enables a Pull-up for USB Charger Detection when set
on the DP pin. (The pull-up is automatically enabled in
UART mode)
ChargerPullupEnDM 5 rd/w/s/c 0b Enables a Pull-up for USB Charger Detection when set
on the DM pin. (The pull-up is automatically enabled in
UART mode)
USB RegOutput 7:6 rd/w/s/c 00b Controls the output voltage of the VBAT to VDD33
regulator in USB mode. When the transceiver is in
Synchronous Mode, Serial Mode, or Low Power Mode,
the regulator output will be the value specified in this
register.
00: 3.3V (default)
01: 3.0V
10: 2.75V
11: 2.5V
Field Name Bit Access Default Description