Datasheet
Table Of Contents
- 1.0 Introduction
- 2.0 USB3320 Pin Locations and Definitions
- 3.0 Limiting Values
- 4.0 Electrical Characteristics
- 4.1 Operating Current
- 4.2 Clock Specifications
- 4.3 ULPI Interface Timing
- 4.4 Digital IO Pins
- 4.5 DC Characteristics: Analog I/O Pins
- 4.6 Dynamic Characteristics: Analog I/O Pins
- 4.7 OTG Electrical Characteristics
- 4.8 USB Audio Switch Characteristics
- 4.9 Regulator Output Voltages and Capacitor Requirement
- 4.10 Piezoelectric Resonator for Internal Oscillator
- 5.0 Architecture Overview
- FIGURE 5-1: USB3320 Internal Block Diagram
- 5.1 ULPI Digital Operation and Interface
- 5.2 USB 2.0 Hi-Speed Transceiver
- 5.3 Bias Generator
- 5.4 Integrated Low Jitter PLL
- 5.5 Internal Regulators and POR
- 5.6 USB On-The-Go (OTG)
- 5.7 USB UART Support
- 5.8 USB Charger Detection Support
- 5.9 USB Audio Support
- 5.10 Reference Frequency Selection
- 6.0 ULPI Operation
- 6.1 Overview
- 6.2 ULPI Register Access
- 6.3 Low Power Mode
- 6.4 Full Speed/Low Speed Serial Modes
- 6.5 Carkit Mode
- 6.6 RID Converter Operation
- 6.7 Headset Audio Mode
- 7.0 ULPI Register Map
- 8.0 Application Notes
- 8.1 Application Diagram
- TABLE 8-1: Component Values in Application Diagrams
- TABLE 8-2: Capacitance Values at VBUS of USB Connector
- FIGURE 8-1: USB3320 Application Diagram (Device, ULPI Output Clock mode, 24MHz)
- FIGURE 8-2: USB3320 Application Diagram (Device, ULPI Input Clock mode, 60MHz)
- FIGURE 8-3: USB3320 Application Diagram (Host or OTG, ULPI Output Clock Mode, 24MHz)
- 8.2 Reference Designs
- 8.3 ESD Performance
- 8.1 Application Diagram
- 9.0 Package Information
- Appendix A: Data Sheet Revision History
- The Microchip Web Site
- Customer Change Notification Service
- Customer Support
- Product Identification System
- Worldwide Sales and Service
2014-2016 Microchip Technology Inc. DS00001792E-page 53
USB3320
7.1.1.10 USB Interrupt Status
Address = 13h (read only)
This register dynamically updates to reflect current status of interrupt sources.
7.1.1.11 USB Interrupt Latch
Address = 14h (read only with auto clear)
Note 7-2 rd: Read Only with auto clear.
7.1.1.12 Debug
Address = 15h (read only)
SessEnd Fall 3 rd/w/s/c 1b Generate an interrupt event notification when SessEnd
changes from high to low.
IdGnd Fall 4 rd/w/s/c 1b Generate an interrupt event notification when IdGnd
changes from high to low.
Reserved 7:5 rd 000b Read only, 0.
Field Name Bit Access Default Description
HostDisconnect 0
rd
0b Current value of the UTMI+ Hi-Speed Hostdisconnect
output. Applicable only in host mode.
VbusValid 1 rd 0b Current value of the UTMI+ Vbusvalid output.
SessValid 2 rd 0b Current value of the UTMI+ SessValid output.
SessEnd 3 rd 0b Current value of the UTMI+ SessEnd output.
IdGnd 4 rd 0b Current value of the UTMI+ IdGnd output.
Reserved 7:5 rd 000b Read only, 0.
Note: The default conditions will match the current status of the comparators. The values shown are for an unat-
tached OTG device.
Field Name Bit Access Default Description
HostDisconnect Latch 0
rd
(Note 7-2)
0b Set to 1b by the transceiver when an unmasked event
occurs on Hostdisconnect. Cleared when this register
is read. Applicable only in host mode.
VbusValid Latch 1
rd
(Note 7-2)
0b Set to 1b by the transceiver when an unmasked event
occurs on VbusValid. Cleared when this register is
read.
SessValid Latch 2
rd
(Note 7-2)
0b Set to 1b by the transceiver when an unmasked event
occurs on SessValid. Cleared when this register is
read.
SessEnd Latch 3rd
(Note 7-2)
0b Set to 1b by the transceiver when an unmasked event
occurs on SessEnd. Cleared when this register is read.
IdGnd Latch 4rd
(Note 7-2)
0b Set to 1b by the transceiver when an unmasked event
occurs on IdGnd. Cleared when this register is read.
Reserved 7:5 rd 000b Read only, 0.
Field Name Bit Access Default Description
Linestate0 0 rd 0b Contains the current value of Linestate[0].
Linestate1 1 rd 0b Contains the current value of Linestate[1].
Reserved 7:2 rd 000000b Read only, 0.
Field Name Bit Access Default Description