Datasheet
Table Of Contents
- 1.0 Introduction
- 2.0 USB3320 Pin Locations and Definitions
- 3.0 Limiting Values
- 4.0 Electrical Characteristics
- 4.1 Operating Current
- 4.2 Clock Specifications
- 4.3 ULPI Interface Timing
- 4.4 Digital IO Pins
- 4.5 DC Characteristics: Analog I/O Pins
- 4.6 Dynamic Characteristics: Analog I/O Pins
- 4.7 OTG Electrical Characteristics
- 4.8 USB Audio Switch Characteristics
- 4.9 Regulator Output Voltages and Capacitor Requirement
- 4.10 Piezoelectric Resonator for Internal Oscillator
- 5.0 Architecture Overview
- FIGURE 5-1: USB3320 Internal Block Diagram
- 5.1 ULPI Digital Operation and Interface
- 5.2 USB 2.0 Hi-Speed Transceiver
- 5.3 Bias Generator
- 5.4 Integrated Low Jitter PLL
- 5.5 Internal Regulators and POR
- 5.6 USB On-The-Go (OTG)
- 5.7 USB UART Support
- 5.8 USB Charger Detection Support
- 5.9 USB Audio Support
- 5.10 Reference Frequency Selection
- 6.0 ULPI Operation
- 6.1 Overview
- 6.2 ULPI Register Access
- 6.3 Low Power Mode
- 6.4 Full Speed/Low Speed Serial Modes
- 6.5 Carkit Mode
- 6.6 RID Converter Operation
- 6.7 Headset Audio Mode
- 7.0 ULPI Register Map
- 8.0 Application Notes
- 8.1 Application Diagram
- TABLE 8-1: Component Values in Application Diagrams
- TABLE 8-2: Capacitance Values at VBUS of USB Connector
- FIGURE 8-1: USB3320 Application Diagram (Device, ULPI Output Clock mode, 24MHz)
- FIGURE 8-2: USB3320 Application Diagram (Device, ULPI Input Clock mode, 60MHz)
- FIGURE 8-3: USB3320 Application Diagram (Host or OTG, ULPI Output Clock Mode, 24MHz)
- 8.2 Reference Designs
- 8.3 ESD Performance
- 8.1 Application Diagram
- 9.0 Package Information
- Appendix A: Data Sheet Revision History
- The Microchip Web Site
- Customer Change Notification Service
- Customer Support
- Product Identification System
- Worldwide Sales and Service
USB3320
DS00001792E-page 50 2014-2016 Microchip Technology Inc.
7.1.1 ULPI REGISTER SET
The following registers are used for the ULPI interface.
7.1.1.1 Vendor ID Low
Address = 00h (read only)
7.1.1.2 Vendor ID High
Address = 01h (read only)
7.1.1.3 Product ID Low
Address = 02h (read only)
7.1.1.4 Product ID High
Address = 03h (read only)
7.1.1.5 Function Control
Address = 04-06h (read), 04h (write), 05h (set), 06h (clear)
Field Name Bit Access Default Description
Vendor ID Low 7:0 rd 24h Microchip Vendor ID
Field Name Bit Access Default Description
Vendor ID High 7:0 rd 04h Microchip Vendor ID
Field Name Bit Access Default Description
Product ID Low 7:0 rd 07h Microchip Product ID
Field Name Bit Access Default Description
Product ID High 7:0 rd 00h Microchip Product ID
Field Name Bit Access Default Description
XcvrSelect[1:0] 1:0 rd/w/s/c 01b Selects the required transceiver speed.
00b: Enables HS transceiver
01b: Enables FS transceiver
10b: Enables LS transceiver
11b: Enables FS transceiver for LS packets (FS
preamble automatically pre-pended)
TermSelect 2 rd/w/s/c 0b Controls the DP and DM termination depending on
XcvrSelect, OpMode, DpPulldown, and DmPulldown.
The DP and DM termination is detailed in Table 5- 1.
OpMode 4:3 rd/w/s/c 00b Selects the required bit encoding style during transmit.
00b: Normal Operation
01b: Non-Driving
10b: Disable bit-stuff and NRZI encoding
11b: Reserved
Reset 5 rd/w/s/c 0b Active high transceiver reset. This reset does not reset
the ULPI interface or register set. Automatically clears
after reset is complete.