Datasheet
Table Of Contents
- 1.0 Introduction
- 2.0 USB3320 Pin Locations and Definitions
- 3.0 Limiting Values
- 4.0 Electrical Characteristics
- 4.1 Operating Current
- 4.2 Clock Specifications
- 4.3 ULPI Interface Timing
- 4.4 Digital IO Pins
- 4.5 DC Characteristics: Analog I/O Pins
- 4.6 Dynamic Characteristics: Analog I/O Pins
- 4.7 OTG Electrical Characteristics
- 4.8 USB Audio Switch Characteristics
- 4.9 Regulator Output Voltages and Capacitor Requirement
- 4.10 Piezoelectric Resonator for Internal Oscillator
- 5.0 Architecture Overview
- FIGURE 5-1: USB3320 Internal Block Diagram
- 5.1 ULPI Digital Operation and Interface
- 5.2 USB 2.0 Hi-Speed Transceiver
- 5.3 Bias Generator
- 5.4 Integrated Low Jitter PLL
- 5.5 Internal Regulators and POR
- 5.6 USB On-The-Go (OTG)
- 5.7 USB UART Support
- 5.8 USB Charger Detection Support
- 5.9 USB Audio Support
- 5.10 Reference Frequency Selection
- 6.0 ULPI Operation
- 6.1 Overview
- 6.2 ULPI Register Access
- 6.3 Low Power Mode
- 6.4 Full Speed/Low Speed Serial Modes
- 6.5 Carkit Mode
- 6.6 RID Converter Operation
- 6.7 Headset Audio Mode
- 7.0 ULPI Register Map
- 8.0 Application Notes
- 8.1 Application Diagram
- TABLE 8-1: Component Values in Application Diagrams
- TABLE 8-2: Capacitance Values at VBUS of USB Connector
- FIGURE 8-1: USB3320 Application Diagram (Device, ULPI Output Clock mode, 24MHz)
- FIGURE 8-2: USB3320 Application Diagram (Device, ULPI Input Clock mode, 60MHz)
- FIGURE 8-3: USB3320 Application Diagram (Host or OTG, ULPI Output Clock Mode, 24MHz)
- 8.2 Reference Designs
- 8.3 ESD Performance
- 8.1 Application Diagram
- 9.0 Package Information
- Appendix A: Data Sheet Revision History
- The Microchip Web Site
- Customer Change Notification Service
- Customer Support
- Product Identification System
- Worldwide Sales and Service
2014-2016 Microchip Technology Inc. DS00001792E-page 49
USB3320
7.0 ULPI REGISTER MAP
7.1 ULPI Register Array
The USB3320 Transceiver implements all of the ULPI registers detailed in the ULPI revision 1.1 specification. The com-
plete USB3320 ULPI register set is shown in Table 7-1. All registers are 8 bits. This table also includes the default state
of each register upon POR or de-assertion of RESETB, as described in Section 5.5.2. The RESET bit in the Function
Control Register does not reset the bits of the ULPI register array. The Link should not read or write to any registers not
listed in this table.
The USB3320 supports extended register access. The immediate register set (00-3Fh) can be accessed through either
a immediate address or an extended register address.
Note 7-1 Dynamically updates to reflect current status of interrupt sources.
TABLE 7-1: ULPI REGISTER MAP
Register Name
Default
State
Address (6bit)
Read Write Set Clear
Vendor ID Low 24h00h---
Vendor ID High 04h01h---
Product ID Low 07h02h---
Product ID High 00h03h---
Function Control 41h 04-06h 04h 05h 06h
Interface Control 00h 07-09h 07h 08h 09h
OTG Control 06h 0A-0Ch 0Ah 0Bh 0Ch
USB Interrupt Enable Rising 1Fh 0D-0Fh 0Dh 0Eh 0Fh
USB Interrupt Enable Falling 1Fh 10-12h 10h 11h 12h
USB Interrupt Status (Note 7-1) 00h13h---
USB Interrupt Latch 00h14h---
Debug 00h15h---
Scratch Register 00h 16-18h 16h 17h 18h
Carkit Control 00h 19-1Bh 19h 1Ah 1Bh
Reserved 00h 1Ch
Carkit Interrupt Enable 00h 1D-1Fh 1Dh 1Eh 1Fh
Carkit Interrupt Status 00h20h---
Carkit Interrupt Latch 00h21h---
Reserved 00h 22-30h
HS TX Boost 00h 31h 31h - -
Reserved 00h 32h 32h - -
Headset Audio Mode 00h 33h 33h - -
Reserved 00h 34-35h
Vendor Rid Conversion 00h 36-38h 36h 37h 38h
USB IO & Power Management 04h 39-3Bh 39h 3Ah 3Bh
Reserved 00h 3C-3Fh