Datasheet

 2014-2016 Microchip Technology Inc. DS00001792E-page 45
USB3320
In some cases, a Link may be software configured and not have control of its STP pin until after the transceiver has
started. In this case, the USB3320 has in internal pull-up on the STP input pad which will pull STP high while the Link’s
STP output is tri-stated. The STP pull-up resistor is enabled on POR and can be disabled by setting the InterfacePro-
tectDisable bit 7 of the Interface Control register.
The STP pull-up resistor will pull-up the Link’s STP input high until the Link configures and drives STP high. After the
Link completes its start-up, STP can be synchronously driven low.
A Link design which drives STP high during POR can disable the pull-up resistor on STP by setting InterfaceProtect-
Disable bit to 1. A motivation for this is to reduce the suspend current. In Low Power Mode, STP is held low, which would
draw current through the pull-up resistor on STP.
6.3.3.2 Warm Reset
Designers should also consider the case of a warm restart of a Link with a transceiver in Low Power Mode. After the
transceiver enters Low Power Mode, DIR is asserted and the clock is stopped. The USB3320 looks for STP to be
asserted to re-start the clock and then resume normal synchronous operation.
Should the USB3320 be suspended in Low Power Mode, and the Link receives a hardware reset, the transceiver must
be able to recover from Low Power Mode and start its clock. If the Link asserts STP on reset, the transceiver will exit
Low Power Mode and start its clock.
If the Link does not assert STP on reset, the interface protection pull-up can be used. When the Link is reset, its STP
output will tri-state and the pull-up resistor will pull STP high, signaling the transceiver to restart its clock.
6.3.4 MINIMIZING CURRENT IN LOW POWER MODE
In order to minimize the suspend current in Low Power Mode, the OTG comparators can be disabled to reduce suspend
current. In Low Power Mode, the VbusVld and SessEnd comparators are not needed and can be disabled by clearing
the associated bits in both the USB Interrupt Enable Rising and USB Interrupt Enable Falling registers. By disabling the
interrupt in BOTH the rise and fall registers, the SessEnd and VbusVld comparators are turned off. The IdFloatRise and
IdFloatFall bits in Carkit Interrupt Enable register should also be disabled if they were set. When exiting Low Power
Mode, the Link should immediately re-enable the VbusVld and SessEnd comparators if host or OTG functionality is
required.
In addition to disabling the OTG comparators in Low Power Mode, the Link may choose to disable the Interface Protect
Circuit. By setting the InterfaceProtectDisable bit high in the Interface Control register, the Link can disable the pull-up
resistor on STP. When RESETB is low the Interface Protect Circuit will be disabled.
6.4 Full Speed/Low Speed Serial Modes
The USB3320 includes two serial modes to support legacy Links which use either the 3pin or 6pin serial format. To enter
either serial mode, the Link will need to write a 1 to the 6-pin FsLsSerialMode or the 3-pin FsLsSerialMode bits in the
Interface control register. Serial Mode may be used to conserve power when attached to a device that is not capable of
operating in Hi-Speed.
The serial modes are entered in the same manner as the entry into Low Power Mode. The Link writes the Interface
Control register bit for the specific serial mode. The USB3320 will assert DIR and shut off the clock after at least five
clock cycles. Then the data bus goes to the format of the serial mode selected. Before entering Serial Mode the Link
must set the ULPI transceiver to the appropriate mode as defined in Tab le 5- 1.
In ULPI Output Clock Mode, the transceiver will shut off the 60MHz clock to conserve power. Should the Link need the
60MHz clock to continue during the serial mode of operation, the ClockSuspendM bit[3] of the Interface Control Register
should be set before entering a serial mode. If set, the 60 MHz clock will be present during serial modes.
In serial mode, interrupts are possible from unmasked sources. The state of each interrupt source is sampled prior to
the assertion of DIR and this is compared against the asynchronous level from interrupt source.
Exiting the serial modes is the same as exiting Low Power Mode. The Link must assert STP to signal the transceiver to
exit serial mode. When the transceiver can accept a command, DIR is de-asserted and the transceiver will wait until the
Link de-asserts STP to resume synchronous ULPI operation. The RESETB pin can also be pulsed low to reset the
USB3320 and return it to Synchronous Mode.